forked from M-Labs/artiq
drtio: reorganize RX synchronizers
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e5de5ef473
commit
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@ -1,7 +1,6 @@
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from types import SimpleNamespace
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from migen import *
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from migen.genlib.cdc import ElasticBuffer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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@ -10,6 +9,7 @@ from artiq.gateware.rtio.input_collector import *
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from artiq.gateware.drtio import (link_layer, aux_controller,
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rt_packet_satellite, rt_errors_satellite,
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rt_packet_master, rt_controller_master)
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from artiq.gateware.drtio.rx_synchronizer import GenericRXSynchronizer
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class ChannelInterface:
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@ -29,29 +29,6 @@ class TransceiverInterface(AutoCSR):
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self.channels = channel_interfaces
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class GenericRXSynchronizer(Module):
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"""Simple RX synchronizer based on the portable Migen elastic buffer.
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Introduces timing non-determinism in the satellite RX path, e.g.
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echo_request/echo_reply RTT and TSC sync, but useful for testing.
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"""
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def __init__(self):
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self.signals = []
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def resync(self, signal):
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synchronized = Signal.like(signal, related=signal)
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self.signals.append((signal, synchronized))
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return synchronized
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def do_finalize(self):
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eb = ElasticBuffer(sum(len(s[0]) for s in self.signals), 4, "rtio_rx", "rtio")
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self.submodules += eb
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self.comb += [
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eb.din.eq(Cat(*[s[0] for s in self.signals])),
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Cat(*[s[1] for s in self.signals]).eq(eb.dout)
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]
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class DRTIOSatellite(Module):
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def __init__(self, chanif, channels, rx_synchronizer=None, fine_ts_width=3,
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lane_count=8, fifo_depth=128):
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@ -1,4 +1,28 @@
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from migen import *
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from migen.genlib.cdc import ElasticBuffer
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class GenericRXSynchronizer(Module):
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"""Simple RX synchronizer based on the portable Migen elastic buffer.
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Introduces timing non-determinism in the satellite RX path, e.g.
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echo_request/echo_reply RTT and TSC sync, but useful for testing.
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"""
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def __init__(self):
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self.signals = []
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def resync(self, signal):
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synchronized = Signal.like(signal, related=signal)
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self.signals.append((signal, synchronized))
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return synchronized
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def do_finalize(self):
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eb = ElasticBuffer(sum(len(s[0]) for s in self.signals), 4, "rtio_rx", "rtio")
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self.submodules += eb
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self.comb += [
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eb.din.eq(Cat(*[s[0] for s in self.signals])),
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Cat(*[s[1] for s in self.signals]).eq(eb.dout)
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]
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class XilinxRXSynchronizer(Module):
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@ -21,7 +21,7 @@ from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.xilinx_rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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@ -33,7 +33,7 @@ from artiq.gateware import remote_csr
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.xilinx_rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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