artiq/artiq/test/coredevice
Etienne Wodey e8730a7e14 coredevice: adf5356: add test for failed PLL lock
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-11-10 10:49:22 +08:00
..
__init__.py test/*/: add missing __init__.py 2016-01-18 14:22:40 -07:00
test_ad9910.py ad9910: add ram conversion tooling and unittests 2019-02-21 15:59:52 +00:00
test_adf5356.py coredevice: adf5356: add test for failed PLL lock 2020-11-10 10:49:22 +08:00
test_analyzer.py test_analyzer: configure loop_out as output 2020-07-16 19:28:58 +08:00
test_cache.py test: skip CacheTest.test_borrow on Zynq 2020-08-06 10:54:30 +08:00
test_compile.py consistent use of 'class name' terminology to select a class within an experiment file. Closes #1348 2019-09-09 15:16:33 +08:00
test_edge_counter.py Add gateware input event counter 2019-01-15 10:55:07 +00:00
test_embedding.py compiler: Raise exception on failed assert()s rather than panic 2020-11-10 00:51:24 +01:00
test_i2c.py test: skip NonexistentI2CBus if I2C is not supported 2020-09-01 16:47:04 +08:00
test_moninj.py test_moninj: set loop_out as output 2020-07-19 17:59:43 +08:00
test_numpy.py test: omit unavailable math functions on OR1K 2020-08-12 15:01:13 +08:00
test_performance.py Revert "test: temporarily disable test_async_throughput" 2020-09-03 14:19:55 +08:00
test_phaser.py phaser: add hitl test exercising the complete API 2020-09-22 15:35:19 +00:00
test_portability.py tests: fix coredevice tests after implementing scheduler defaults 2019-03-22 07:27:55 +08:00
test_rtio.py test: relax test_dma_playback_time on Zynq 2020-09-11 11:21:45 +08:00
test_spi.py test_spi: move to new spi2 core 2018-02-21 19:41:05 +01:00
test_stress.py test: only test_rpc_timing actually requires ARTIQ_LOW_LATENCY 2019-04-24 11:22:07 +08:00
test_urukul.py urukul: expand attenuator HITL unittests 2018-12-07 21:06:12 +00:00