Etienne Wodey
e8730a7e14
coredevice: adf5356: add test for failed PLL lock
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-11-10 10:49:22 +08:00
Etienne Wodey
3844123c13
coredevice: adf5356: add enable/disable and power setting for outA
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-11-10 10:49:22 +08:00
Etienne Wodey
61dc2b8b64
coredevice: adf5356: add some tests
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-11-10 10:49:22 +08:00
David Nadlinger
4f311e7448
compiler: Raise exception on failed assert()s rather than panic
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This allows assert() to be used on Zynq, where abort() is not
currently implemented for kernels. Furthermore, this is arguably
the more natural implementation of assertions on all kernel targets
(i.e. where embedding into host Python is used), as it matches host
Python behavior, and the exception information actually makes it to
the user rather than leading to a ConnectionClosed error.
Since this does not implement printing of the subexpressions, I
left the old print+abort implementation as default for the time
being.
The lit/integration/instance.py diff isn't just a spurious change;
the exception-based assert implementation exposes a limitation in
the existing closure lifetime tracking algorithm (which is not
supposed to be what is tested there).
GitHub: Fixes #1539 .
2020-11-10 00:51:24 +01:00
David Nadlinger
f0ec987d23
test/coredevice: Avoid NumPy deprecation warning
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Jagged arrays are no longer silently inferred as dtype=object,
as per NEP-34.
The compiler ndarray (re)implementation is unchanged, so the
test still fails.
2020-11-09 23:53:50 +01:00
David Nadlinger
d672d2fc35
test/coredevice: Fixup NumPy references
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This fixes a copy/paste refactoring mistake from d5f90f6c9
2020-10-20 02:49:05 +02:00
David Nadlinger
d5f90f6c9f
compiler: Fix quoting of multi-dimensional arrays
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GitHub: Fixes m-labs/artiq#1523 .
2020-10-20 01:40:14 +02:00
50b4eb4840
Merge branch 'master' into phaser
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* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
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2020-09-22 16:02:25 +00:00
ad096f294c
phaser: add hitl test exercising the complete API
2020-09-22 15:35:19 +00:00
bff611a888
test: relax test_dma_playback_time on Zynq
2020-09-11 11:21:45 +08:00
47e88dfcbe
Revert "test: temporarily disable test_async_throughput"
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This reverts commit f0289d49ab
2020-09-03 14:19:55 +08:00
4398a2d5fa
test: relax loopback gate timing
2020-09-01 17:50:09 +08:00
f0289d49ab
test: temporarily disable test_async_throughput
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M-Labs/artiq-zynq#104
2020-09-01 17:49:40 +08:00
8d5dc0ad2a
test: relax test_pulse_rate on Zynq
2020-09-01 17:08:26 +08:00
f294d039b3
test: skip NonexistentI2CBus if I2C is not supported
2020-09-01 16:47:04 +08:00
69f0699ebd
test: improved test_performance
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1. Added tests for small payload.
2. Added statistics.
2020-08-28 14:58:34 +08:00
cfddc13294
test: fixed test_performance
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Added more tests and use normal rpc instead of async rpc.
Async RPC does not represent the real throughput which is limited by the
hardware and the network. Normal RPC which requires a response from the
remote is closer to real usecases.
2020-08-26 14:17:06 +08:00
a46573e97a
Revert "test: set uart log level to INFO for DMA tests"
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This reverts commit b05cbcbc24
2020-08-13 12:44:33 +08:00
b05cbcbc24
test: set uart log level to INFO for DMA tests
2020-08-13 12:24:57 +08:00
48008eaf5f
test: omit unavailable math functions on OR1K
2020-08-12 15:01:13 +08:00
David Nadlinger
c6f0c4dca4
test/coredevice: Ignore jagged 2D array embedding test for now
2020-08-10 00:23:38 +01:00
David Nadlinger
778f2cf905
compiler: Fix numpy.full, implement for >1D
2020-08-09 23:46:45 +01:00
David Nadlinger
d35f659d25
compiler: Add additional math fns available from Rust libm
2020-08-09 20:09:43 +01:00
David Nadlinger
a39bd69ca4
compiler: Implement numpy.rint() using llvm.round()
2020-08-09 19:44:58 +01:00
David Nadlinger
ae47d4c0ec
test/coredevice: Add host/device consistency checks for NumPy math
2020-08-09 19:15:43 +01:00
David Nadlinger
8783ba2072
compiler/firmware: RPCs for ndarrays
2020-08-09 17:08:43 +01:00
5f36e49f91
test_rtio: make DMA test generic wrt TTL channel
2020-08-06 16:36:14 +08:00
e3c5775584
test: skip CacheTest.test_borrow on Zynq
2020-08-06 10:54:30 +08:00
709026d945
test: relax device_to_host_rate
2020-07-30 17:46:22 +08:00
553a49e194
test_moninj: set loop_out as output
2020-07-19 17:59:43 +08:00
8510bf4e55
test_analyzer: configure loop_out as output
2020-07-16 19:28:58 +08:00
85b5a04acf
test: print transfer rates in MiB/s
2020-07-07 17:28:47 +08:00
13501115f6
test: remove watchdog test ( #1458 )
2020-07-07 17:28:47 +08:00
98caaebade
consistent use of 'class name' terminology to select a class within an experiment file. Closes #1348
2019-09-09 15:16:33 +08:00
4cc9bd33ce
test: only test_rpc_timing actually requires ARTIQ_LOW_LATENCY
2019-04-24 11:22:07 +08:00
David Nadlinger
cd7a5a3683
firmware: Fix kernel RPC handling of zero-size values (e.g. empty arrays)
2019-03-31 18:33:44 +01:00
David Nadlinger
236b30ac5f
coredevice: Add test for recent kernel RPC fixes
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This covers all three (de)serialisation fixes.
2019-03-31 18:25:56 +01:00
7cdcaf0d00
tests: fix coredevice tests after implementing scheduler defaults
2019-03-22 07:27:55 +08:00
aee8965897
ad9910: add ram conversion tooling and unittests
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-21 15:59:52 +00:00
ec6588174b
ad9910: add ram operation unittests
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-21 15:14:32 +00:00
90c9fa446f
test: add array transfer test
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200 kB/s, more than a factor of 10 slower than the bare string transfer
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-28 14:30:44 +00:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
088530604e
test_ad9910: relax tests
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* tune_sync_delay: the opposite IO_UPDATE to SYNC_CLK alignment may not be perfectly
mis-aligned
* set_mu_speed: seems to be slower on the buildbot
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 17:27:42 +00:00
d90eb3ae88
ad9910: add read64()
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:27:00 +00:00
baf88050fd
urukul: expand attenuator HITL unittests
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* read back with cleared backing state
* individual channel settings
* check backing state
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:06:12 +00:00
6aa341bc44
test_loopback_gate_timing: fix lat_offset
2018-12-02 20:52:32 +08:00
7f55376c75
test_loopback_gate_timing: print input timing for debugging
2018-12-01 18:09:53 +08:00
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
69e699c7bd
ttl: compensate for SED latency in input gating
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Closes #1137
2018-11-17 22:10:20 +08:00
1b841805f6
Merge branch 'master' into new
2018-11-16 15:20:32 +08:00
