forked from M-Labs/artiq
test: skip CacheTest.test_borrow on Zynq
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@ -1,5 +1,6 @@
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from artiq.experiment import *
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from artiq.coredevice.exceptions import CacheError
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from artiq.compiler.targets import CortexA9Target
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from artiq.test.hardware_testbench import ExperimentCase
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@ -40,6 +41,8 @@ class CacheTest(ExperimentCase):
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def test_borrow(self):
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exp = self.create(_Cache)
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if exp.core.target_cls == CortexA9Target:
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self.skipTest("Zynq port memory management does not need CacheError")
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exp.put("x4", [1, 2, 3])
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with self.assertRaises(CacheError):
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exp.get_put("x4", [])
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