Commit Graph

287 Commits

Author SHA1 Message Date
whitequark
b6e2613f77 runtime: avoid spurious error messages. 2015-08-07 11:03:36 +03:00
whitequark
b5cf1e395d runtime: avoid race condition when running kernel.
Also, don't bother passing kernel name: entry point is already
recorded in DT_INIT when the kernel is linked.
2015-08-07 08:51:33 +03:00
whitequark
98cd4288c1 artiq_personality: cast exception params so that %lld is always valid. 2015-08-06 08:25:53 +03:00
whitequark
722dfef97b artiq_personality: simplify. 2015-08-06 07:59:15 +03:00
whitequark
62fdc75d2d Integrate libdyld and libunwind.
It is currently possible to run the idle experiment, and it
can raise and catch exceptions, but exceptions are not yet
propagated across RPC boundaries.
2015-08-02 15:43:03 +03:00
whitequark
6db93b34e8 artiq_personality: port to device. 2015-08-02 06:34:11 +03:00
whitequark
aae2923c4c runtime: add lognonl{,_va} functions.
The kernels have print(), which prints aggregates (such as
arrays) piece-by-piece, and newlines would interfere.
2015-08-02 06:33:12 +03:00
whitequark
cd294e2986 artiq_personality: avoid unaligned loads. 2015-08-02 06:28:58 +03:00
whitequark
697b78ddf2 Rename {kserver → net_server}.{c,h}. 2015-07-30 13:45:57 +03:00
whitequark
fd46d8b11e Merge branch 'master' into new-py2llvm 2015-07-29 12:52:19 +03:00
whitequark
c40ae9dbd3 MiSoC is not built with -fPIC anymore, remove support code for that. 2015-07-29 12:40:46 +03:00
67715f0d2e pipistrello: only put serdes on the lower ttls
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
2015-07-28 12:54:31 -06:00
9dfbf07743 pipistrello: use 4x serdes for rtio ttl
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
2015-07-28 12:54:27 -06:00
8e391e2661 kc705: generate 10MHz clock on GPIO SMA
For SynthNV and input tests.
2015-07-28 18:56:47 +08:00
1809a70f5c Revert "pipistrello: use 4x serdes for rtio ttl"
This reverts commit 8e92cc91f5.

Broken. Will revisit.
2015-07-27 23:39:35 -06:00
f0a7078336 Revert "rtiocrg.c: pipistrello also has pll_reset"
This reverts commit bdee914828.
2015-07-27 22:18:45 -06:00
bdee914828 rtiocrg.c: pipistrello also has pll_reset 2015-07-27 22:14:42 -06:00
e95b06e96d pipistrello: tie unused dds.p low 2015-07-27 21:48:56 -06:00
8e92cc91f5 pipistrello: use 4x serdes for rtio ttl 2015-07-27 21:29:50 -06:00
ae3a52c49c runtime: fix KERNELCPU_PAYLOAD_ADDRESS 2015-07-28 02:12:14 +08:00
whitequark
eec4a2d2d2 Update buildsystem to track -fPIC and ranlib removal in MiSoC. 2015-07-27 21:10:46 +03:00
0cd74533ca runtime: more explicit message about startup clock failure 2015-07-28 00:38:38 +08:00
7feaca7c7c runtime: allow selecting external clock at startup 2015-07-28 00:19:07 +08:00
09d837e4ba runtime: monitor RTIO clock status 2015-07-28 00:05:24 +08:00
299bc1cb7e kc705: output divided-by-2 RTIO clock 2015-07-27 20:46:44 +08:00
256e99f0d7 kc705: crg cleanup 2015-07-27 20:31:37 +08:00
2a95e866aa kc705: use 8X SERDES RTIO PHY 2015-07-27 20:12:17 +08:00
fe57308e71 runtime: support for RTIO PLL 2015-07-27 20:11:31 +08:00
whitequark
244ace19e1 Add artiq_raise_from_c macro. 2015-07-27 13:56:18 +03:00
whitequark
edffb40ef2 On uncaught exception, execute finally clauses and collect backtrace. 2015-07-27 13:51:24 +03:00
whitequark
2939d4f0f3 Add tests for finally clause and reraising. 2015-07-27 12:36:21 +03:00
whitequark
a83e7e2248 Add tests for exceptional control flow. 2015-07-27 10:22:28 +03:00
whitequark
7c77dd317a Implement __artiq_personality. 2015-07-27 09:10:20 +03:00
117b361a06 Merge branch 'master' of github.com:m-labs/artiq 2015-07-27 11:42:29 +08:00
3573fd02a6 targets/kc705: add TIG constraints for ISE 2015-07-27 10:58:19 +08:00
fe6a5c42df rtio: remove unused clk_freq argument 2015-07-27 10:57:15 +08:00
d3f05e414a runtime: account for RTIO_FINE_TS_WIDTH in time buffers 2015-07-27 10:50:25 +08:00
whitequark
bb5fe60137 Implement exception raising. 2015-07-27 05:46:43 +03:00
whitequark
ef4a06a270 Merge branch 'master' into new-py2llvm 2015-07-27 04:57:32 +03:00
whitequark
14c7b15785 Add a test harness for exceptions.
The libunwind.h is duplicated here so that it would be possible
to test the Python parts without pulling in misoc.
2015-07-27 04:18:12 +03:00
d65d303ac6 pipistrello: remove unused constraint kwarg 2015-07-26 17:39:07 -06:00
whitequark
1d9f40833d Update ldscripts with -fPIC support. 2015-07-26 16:16:48 +03:00
aba2d3f112 runtime: process essential kernel CPU messages at all time 2015-07-25 16:26:04 +08:00
34aacd3c5f complete AD9914 support (no programmable modulus, untested) 2015-07-08 17:22:43 +02:00
8a33d8c868 never stop RTIO counter 2015-07-07 15:29:38 +02:00
d20fb5abb2 remove workaround 2015-07-07 13:46:14 +02:00
959ba99f1c pipistrello: try simpler constraints 2015-07-04 21:08:28 -06:00
753d61b38f complete support for TTL clock generator 2015-07-04 18:36:01 +02:00
0a9f9093f7 kc705: fix ttl15 2015-07-02 20:02:05 +02:00
2881d5f00a gateware: add RTIO clock generator 2015-07-02 18:20:26 +02:00