forked from M-Labs/artiq
pipistrello: only put serdes on the lower ttls
this setup is getting a bit power hungry. pmt0, 1 (rtio channels 0, 1): 4x in and out ttl0, 1 (rtio channels 2, 3): 4x out ttl2 (rtio channel 4): 8x out
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@ -145,8 +145,15 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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# ttl2 can run on a 8x serdes if xtrig is not used
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for i in range(15):
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phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
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self.rtio_crg.rtiox4_stb)
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if i in (0, 1):
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phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
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self.rtio_crg.rtiox4_stb)
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elif i in (2,):
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phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
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self.rtio_crg.rtiox8_stb)
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else:
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
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