srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

pipistrello: only put serdes on the lower ttls

Browse Source 
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
This commit is contained in:
Robert Jördens 2015-07-28 12:50:34 -06:00
parent fb339d294e
commit 67715f0d2e
1 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
soc/targets/artiq_pipistrello.py
View File

@ -145,8 +145,15 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
# ttl2 can run on a 8x serdes if xtrig is not used
for i in range(15):
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
if i in (0, 1):
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
elif i in (2,):
phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
self.rtio_crg.rtiox8_stb)
else:
phy = ttl_simple.Output(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))