|
|
f03ae5e5b0
|
soc/rtio: separate PHY, add OE and fine timestamp in FIFO
|
2014-07-24 23:50:20 -06:00 |
|
|
|
005d66c7cd
|
soc/dds: fix timing
|
2014-07-22 17:44:41 -06:00 |
|
|
|
2358b218bf
|
soc: add DDS interface core
|
2014-07-22 11:37:53 -06:00 |
|
|
|
5573cf3688
|
soc: add tester IO
|
2014-07-22 10:45:59 -06:00 |
|
|
|
ede3667fd3
|
soc/target: use only 8 TTL channels for now
|
2014-07-20 18:38:41 -06:00 |
|
|
|
3b4bb41a19
|
add basic output-only untested RTIO core
|
2014-07-16 19:13:11 -06:00 |
|
|
|
d804f1199e
|
soc: add LED
|
2014-07-05 22:44:20 +02:00 |
|
|
|
6072f0c42f
|
Basic SoC and runtime design
|
2014-07-04 17:49:08 +02:00 |
|
