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4879 Commits

Author SHA1 Message Date
Chris Ballance 223501f811 master: use epoch time for timestamps (closes #726) 2017-08-03 10:30:31 +01:00
Chris Ballance eabca1f311 master: correct example datestring in help 2017-08-03 10:12:52 +01:00
Chris Ballance 810bb69989 master: rotate logs at midnight, rather than on log size 2017-08-03 00:31:04 +01:00
Sebastien Bourdeauducq 2998372d08 browser,dashboard: delete MDI subwindows when they are closed 2017-07-29 20:36:38 +08:00
mntng 692dc0803b test: add test for SPI core using SD card 2017-07-28 19:10:44 +08:00
Sebastien Bourdeauducq 3778f93991 README: update credits/roles 2017-07-25 13:34:00 +08:00
Sebastien Bourdeauducq 3ae1c4f7f7 manual: add note about updating conda (#785) 2017-07-25 13:05:43 +08:00
Sebastien Bourdeauducq df4f38a1e4 kc705: add pullup on SD card MISO 2017-07-24 22:26:16 +08:00
Sebastien Bourdeauducq 7eed4e7b6c synchronize introduction.rst with README 2017-07-22 00:41:59 +08:00
dhslichter 61b0ad1982 Update README links 2017-07-22 00:11:16 +08:00
Sebastien Bourdeauducq 189020344c spi: fix typo in doc 2017-07-20 22:18:21 +08:00
Sebastien Bourdeauducq d0b21a8e85 manual: add short description of drivers, with replace support information. Closes #777 2017-07-20 12:01:29 +08:00
Robert Jördens 471605ec1e pdq: move to https://github.com/m-labs/pdq 2017-07-19 17:35:28 +02:00
Robert Jördens 5c66b63768 setup.py etc: update license 2017-07-18 11:31:43 +02:00
Sebastien Bourdeauducq 377c776ec8 examples/dma_blink: replay → playback 2017-07-18 14:01:08 +08:00
Sebastien Bourdeauducq 9898681a38 aqctl_corelog: only set logging.DEBUG after the server is set up 
Otherwise asyncio pollutes the log.
 2017-07-18 14:00:06 +08:00
whitequark dd87508a7f Implement forwarding of logs from core device to master. 
Fixes #691.
 2017-07-18 05:31:59 +00:00
whitequark 819440f839 runtime: split log timestamp into secs.micros. 2017-07-18 05:31:59 +00:00
whitequark 9e38132c0a artiq_devtool: don't drop data in unpredictable ways (sigh). 2017-07-18 05:31:59 +00:00
Sebastien Bourdeauducq a201a9abd9 drtio: multilink transceiver interface 2017-07-18 13:27:33 +08:00
Robert Jördens d96c2abe44 pdq: read/write_reg -> get/set_reg 
see also m-labs/pdq#14
 2017-07-17 21:45:46 +02:00
Sebastien Bourdeauducq 9045b4cc19 drtio: initial firmware support for multi-link 2017-07-18 00:40:21 +08:00
Robert Jördens 94ee48860a doc: fix phaser channel number statement 
closes #781
 2017-07-15 20:24:50 +02:00
whitequark d06d53b00d firmware: don't bail out if building not from a git checkout (#783). 2017-07-15 03:16:21 +00:00
Sebastien Bourdeauducq 0253db0421 conda: fix misoc git hash 2017-07-13 19:32:03 +08:00
Sebastien Bourdeauducq 4deb5f6a45 gateware: use new MiSoC Wishbone address system 2017-07-13 19:16:49 +08:00
mntng 40ca951750 kc705: add SPI bus for memory card 
This will be useful for SPI unit tests using a SD card as victim.
 2017-07-12 00:27:44 +08:00
Robert Jördens 298ceafd92 README_PHASER: fix ref_multiplier 2017-07-08 19:44:57 +02:00
Robert Jördens f0841f5489 spline: be really verbose 
closes #773
 2017-07-07 11:43:58 +02:00
Robert Jördens 7b130a2c32 sawg: confirm smooth(order=3) 2017-07-07 11:36:03 +02:00
Robert Jördens 3bc0e32dc0 sawg: advance the timeline on Config access 
c.f. #773 #765
 2017-07-07 11:33:58 +02:00
Robert Jördens 3222f5036f sawg: describe latency matching in detail 2017-07-06 10:06:21 +02:00
whitequark 1e2603572a runtime: fix a bug causing sockets to get stuck in CLOSE-WAIT. 2017-07-05 16:27:36 +00:00
whitequark 86c027e9c5 artiq_flash: don't require binaries to merely restart FPGA. 2017-07-04 18:55:38 +00:00
whitequark ee1d5dbccb runtime: allow a much larger log buffer and avoid hacks. 2017-07-04 18:18:31 +00:00
whitequark 3ab8a4d505 aqctl_corelog: add missing script definition to setup.py. 2017-07-04 18:04:25 +00:00
whitequark 7a5fbc1622 devtool: forward port 1383 (moninj). 2017-07-04 17:54:18 +00:00
whitequark 4e5ea1bbaf dashboard: fix a crash touching moninj without a connection. 2017-07-04 17:53:48 +00:00
Robert Jördens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" 
This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
 2017-07-04 17:55:19 +02:00
Robert Jördens 8e0a1cbdc8 sawg: advance dds 1/2 by one sample group 
closes #772
 2017-07-04 16:51:58 +02:00
Robert Jördens 91ca9fbcad sawg: also give offset some headroom 
closes #771
 2017-07-04 16:50:06 +02:00
Robert Jördens 60809d1cb4 conda: bump misoc (migen change) 2017-07-04 11:58:12 +02:00
Robert Jördens 78d1f0fdf6 sawg: fix PhasedAccu resets 2017-07-04 11:56:21 +02:00
Florent Kermarrec 42476c64a7 conda: bump migen (Record.connect leave_out --> keep/omit) 2017-07-04 11:26:57 +02:00
Florent Kermarrec 2910b1be5e artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect 2017-07-04 10:48:06 +02:00
Robert Jördens 5b26e5de6c conda: bump migen (reset_less cdc) 2017-07-02 15:41:58 +02:00
Sebastien Bourdeauducq d7ad72efa2 doc: point to artiq_flash hardware selection options when writing flash storage. Closes #766 2017-07-02 10:40:52 +08:00
Sebastien Bourdeauducq 838127d914 rtio: break DMA timing path 2017-07-02 10:24:01 +08:00
whitequark ea7549cfa4 compiler: coerce `while` condition to bool. 
Fixes #768.
 2017-07-01 18:59:07 +00:00
Robert Jördens 911ee4a959 rtio: make pipelined logic reset_less 
* latency-corrected counters
* registered error logic
 2017-06-29 12:55:32 +02:00