forked from M-Labs/artiq
gateware: use new MiSoC Wishbone address system
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40ca951750
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4deb5f6a45
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@ -2,7 +2,7 @@ from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import wishbone
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from misoc.cores import mor1kx
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from misoc.integration.soc_core import mem_decoder
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from misoc.integration.wb_slaves import WishboneSlaveManager
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class KernelCPU(Module):
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@ -14,7 +14,7 @@ class KernelCPU(Module):
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# # #
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self._wb_slaves = []
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self._wb_slaves = WishboneSlaveManager(0x80000000)
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# CPU core
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self.clock_domains.cd_sys_kernel = ClockDomain()
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@ -31,16 +31,17 @@ class KernelCPU(Module):
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# DRAM access
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self.wb_sdram = wishbone.Interface()
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self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
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self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
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def get_csrs(self):
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return [self._reset]
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def do_finalize(self):
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self.submodules.wishbonecon = wishbone.InterconnectShared(
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[self.cpu.ibus, self.cpu.dbus], self._wb_slaves, register=True)
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[self.cpu.ibus, self.cpu.dbus],
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self._wb_slaves.get_interconnect_slaves(), register=True)
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def add_wb_slave(self, address_decoder, interface):
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def add_wb_slave(self, origin, length, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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self._wb_slaves.add(origin, length, interface)
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@ -1,6 +1,5 @@
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import os
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from misoc.integration.soc_core import mem_decoder
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from misoc.cores import timer
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from misoc.interconnect import wishbone
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from misoc.integration.builder import *
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@ -23,21 +22,22 @@ class AMPSoC:
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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self.csr_devices.append("kernel_cpu")
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self.submodules.mailbox = Mailbox(size=3)
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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mailbox_size = 3
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self.submodules.mailbox = Mailbox(mailbox_size)
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self.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size,
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self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size,
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self.mailbox.i2)
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self.add_memory_region("mailbox",
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self.mem_map["mailbox"] | 0x80000000, 4)
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self.mem_map["mailbox"] | 0x80000000,
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4*mailbox_size)
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def register_kernel_cpu_csrdevice(self, name, csrs=None):
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if csrs is None:
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csrs = getattr(self, name).get_csrs()
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bank = wishbone.CSRBank(csrs)
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self.submodules += bank
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]),
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bank.bus)
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self.kernel_cpu.add_wb_slave(self.mem_map[name], 4*2**bank.decode_bits, bank.bus)
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self.add_csr_region(name,
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self.mem_map[name] | 0x80000000, 32,
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csrs)
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@ -7,7 +7,6 @@ from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.soc_core import mem_decoder
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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@ -56,7 +55,7 @@ class Master(MiniSoC, AMPSoC):
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.csr_devices.append("drtio")
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self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio.aux_controller.bus)
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self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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@ -6,7 +6,6 @@ from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.builder import *
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from misoc.integration.soc_core import mem_decoder
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from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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@ -61,7 +60,7 @@ class Satellite(BaseSoC):
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self.transceiver, rtio_channels, self.rx_synchronizer)
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self.csr_devices.append("rx_synchronizer")
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self.csr_devices.append("drtio")
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self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio.aux_controller.bus)
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self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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@ -15,7 +15,7 @@ requirements:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.5.dev py_117+gite826cb9
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- misoc 0.6.dev py_22+gite205c2ea
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- misoc 0.6.dev py_32+git207a8d66
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- jesd204b 0.3
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- binutils-or1k-linux >=2.27
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- llvm-or1k
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