spi: fix typo in doc

2017-07-20 22:18:21 +08:00 · 2017-07-20 22:18:21 +08:00 · 189020344c
parent d0b21a8e85
commit 189020344c
1 changed files with 1 additions and 1 deletions
--- a/artiq/coredevice/spi.py
+++ b/artiq/coredevice/spi.py
@ -95,7 +95,7 @@ class SPIMaster:
    def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
        """Set the configuration register.

-        * If ``config.cs_polarity`` == 0 (```cs`` active low, the default),
+        * If ``config.cs_polarity`` == 0 (``cs`` active low, the default),
          "``cs_n`` all deasserted" means "all ``cs_n`` bits high".
        * ``cs_n`` is not mandatory in the pads supplied to the gateware core.
          Framing and chip selection can also be handled independently