forked from M-Labs/artiq
sawg: fix PhasedAccu resets
This commit is contained in:
parent
42476c64a7
commit
78d1f0fdf6
|
@ -74,14 +74,12 @@ class PhasedAccu(Module):
|
|||
|
||||
a = MCM(width, range(parallelism + 1))
|
||||
self.submodules += a
|
||||
z = [Signal(width) for i in range(parallelism)]
|
||||
z = [Signal(width, reset_less=True) for i in range(parallelism)]
|
||||
o = self.o.payload.flatten()
|
||||
for oi in o:
|
||||
oi.reset_less = True
|
||||
load = Signal()
|
||||
clr = Signal()
|
||||
load = Signal(reset_less=True)
|
||||
clr = Signal(reset_less=True)
|
||||
p = Signal.like(self.i.p)
|
||||
f = Signal.like(self.i.f)
|
||||
f = Signal.like(self.i.f, reset_less=True)
|
||||
fp = Signal.like(self.i.f)
|
||||
self.comb += [
|
||||
self.i.ack.eq(self.o.ack),
|
||||
|
|
|
@ -56,6 +56,7 @@ class SplineParallelDUC(Module):
|
|||
]
|
||||
|
||||
assert p.latency == 1
|
||||
accu.i.clr.reset_less = True
|
||||
self.sync += [
|
||||
accu.i.clr.eq(0),
|
||||
If(p.i.stb,
|
||||
|
|
Loading…
Reference in New Issue