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4915b4b5aa
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PEP8
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2014-09-05 12:03:22 +08:00 |
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1ed808e848
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soc/target: share base PPro design with MiSoC
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2014-08-03 12:26:15 +08:00 |
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f03ae5e5b0
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soc/rtio: separate PHY, add OE and fine timestamp in FIFO
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2014-07-24 23:50:20 -06:00 |
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005d66c7cd
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soc/dds: fix timing
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2014-07-22 17:44:41 -06:00 |
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2358b218bf
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soc: add DDS interface core
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2014-07-22 11:37:53 -06:00 |
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5573cf3688
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soc: add tester IO
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2014-07-22 10:45:59 -06:00 |
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ede3667fd3
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soc/target: use only 8 TTL channels for now
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2014-07-20 18:38:41 -06:00 |
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3b4bb41a19
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add basic output-only untested RTIO core
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2014-07-16 19:13:11 -06:00 |
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d804f1199e
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soc: add LED
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2014-07-05 22:44:20 +02:00 |
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6072f0c42f
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Basic SoC and runtime design
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2014-07-04 17:49:08 +02:00 |
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