 Jack-Zheng
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53accc8761
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PCB: finish IO and analog connectors
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2021-06-28 10:40:21 +08:00 |
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Jack-Zheng
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4b15f466a0
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PCB: finish SWD, IIC
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2021-06-25 18:15:56 +08:00 |
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Jack-Zheng
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0e1120d266
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FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
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2021-06-25 16:57:46 +08:00 |
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Jack-Zheng
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2a31c8b3f3
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PCB: finish LVDS routing
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2021-06-24 15:43:31 +08:00 |
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Jack-Zheng
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37941bfc2c
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PCB: finalize component positions and define board shape
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2021-06-22 17:14:32 +08:00 |
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Jack-Zheng
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6535ff5423
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LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
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2021-06-22 16:34:02 +08:00 |
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Jack-Zheng
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1df738664f
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all: update gitignore; remove redundant files
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2021-06-22 09:44:50 +08:00 |
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Jack-Zheng
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982fefd6b5
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all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
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2021-06-21 16:05:17 +08:00 |
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Jack-Zheng
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9bcc9a229b
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TestAutomation: replace messy wires with bus
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2021-06-21 12:10:31 +08:00 |
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Jack-Zheng
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dfe4255a21
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MCU: finish FSMC, PWM
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2021-06-17 10:52:33 +08:00 |
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Jack-Zheng
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5b4801ff74
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FPGA: finish EEM, I2C, CFG, SPI FLASH
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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fc2cb47610
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all: map symbol and footpins
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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da19dad9cd
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init project
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2021-06-16 17:31:36 +08:00 |