occheung/serdes-transceiver
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4 Commits 1 Branch 0 Tags 99 KiB
e6902d1da5
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Author SHA1 Message Date
occheung
e6902d1da5 adjust register-wide bitslip right after slave bitslip 2023-04-24 07:10:18 +08:00
occheung
ff7c892fd6 debug delay tap solver 2023-04-24 06:13:05 +08:00
occheung
e2a8433f83 align master/slave pair 2023-04-24 03:55:01 +08:00
occheung
7f23de0ce8 init 2023-04-23 11:42:18 +08:00