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38388d1136
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conda: bump migen
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2017-09-27 19:02:37 +02:00 |
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5e3cc83842
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sayma_amc: SAWG (untested)
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2017-09-27 18:44:35 +02:00 |
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2604806512
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sayma_rtm: make build dir
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2017-09-27 18:35:46 +02:00 |
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2821f50884
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conda: jesd204b 0.4
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2017-09-27 17:17:04 +02:00 |
|
Florent Kermarrec
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2091c7696a
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artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode
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2017-09-06 09:18:12 +02:00 |
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34ec37ac85
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conda: bump misoc
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2017-09-06 11:09:38 +08:00 |
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2b2b345eb9
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firmware: wait for serwb to be ready before proceeding further
|
2017-09-06 11:07:07 +08:00 |
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33f053cff8
|
libboard: complete but undebugged support for HMC830/7043 programming
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2017-09-06 10:46:02 +08:00 |
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4baf17cebe
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libboard: generate HMC7043 register write list
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2017-09-05 21:46:03 +08:00 |
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091bb28043
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libboard: use libbuild_artiq
|
2017-09-05 21:13:04 +08:00 |
|
|
c5fe2799cf
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conda: bump misoc
|
2017-08-31 13:44:31 +08:00 |
|
|
b609366c6f
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runtime: fix Rust types in RTIO
Previous code assumed all RTIO registers were u32, but this was changed
by misoc c5edcd08.
|
2017-08-31 13:42:32 +08:00 |
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44edba0c65
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firmware: add placeholder code for HMC830/7043 initialization
|
2017-08-31 13:35:47 +08:00 |
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9edff2c520
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remote_csr: interpret length as CSR size, not number of bus words
|
2017-08-31 13:34:48 +08:00 |
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|
0a5904bbaa
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firmware: support for multiple JESD DACs
|
2017-08-31 13:05:48 +08:00 |
|
|
a4144a07c4
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sayma_amc: add converter SPI config defines
|
2017-08-31 13:04:38 +08:00 |
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|
bacf8a1614
|
style
|
2017-08-31 12:52:09 +08:00 |
|
|
5a041c24f3
|
conda: bump misoc
|
2017-08-31 12:17:52 +08:00 |
|
|
d92cca9712
|
artiq_flash: fix target_file handling
|
2017-08-31 12:16:52 +08:00 |
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e652221221
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conda: bump migen and misoc
|
2017-08-31 11:50:32 +08:00 |
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|
ad0a940e2d
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sayma_rtm: hook up DAC SPI
|
2017-08-31 11:48:54 +08:00 |
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f765dc50de
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sayma_rtm: do not keep DACs in reset
|
2017-08-31 11:44:33 +08:00 |
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|
a67659338d
|
sayma: clean up serwb comments
|
2017-08-31 11:42:01 +08:00 |
|
Florent Kermarrec
|
660f9856ec
|
gateware/serwb: add test for phy initialization
|
2017-08-30 17:59:10 +02:00 |
|
Florent Kermarrec
|
9650233007
|
gateware/serwb: change serdes clock domain to serwb_serdes
|
2017-08-30 15:44:44 +02:00 |
|
Florent Kermarrec
|
32ca51faee
|
gateware/targets/sayma_amc_standalone/rtm: use new serwb modules
|
2017-08-30 15:25:20 +02:00 |
|
Florent Kermarrec
|
41d57d64f6
|
gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window
|
2017-08-30 14:40:11 +02:00 |
|
Florent Kermarrec
|
9ba50098a8
|
gateware/test/serwb: use unittest for in test_etherbone
|
2017-08-29 17:31:01 +02:00 |
|
Florent Kermarrec
|
7d7f6be7ce
|
gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction
|
2017-08-29 16:41:29 +02:00 |
|
Florent Kermarrec
|
60ad36e7d6
|
gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready
|
2017-08-29 13:43:26 +02:00 |
|
Florent Kermarrec
|
89558e2653
|
gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
|
2017-08-29 13:38:52 +02:00 |
|
|
26a11a296c
|
sayma_rtm: drive DAC control signals
|
2017-08-26 16:57:02 -07:00 |
|
|
d609c67cbd
|
sayma_rtm: set clock mux pins
|
2017-08-26 16:48:10 -07:00 |
|
|
9194402ea5
|
sayma_rtm: expose HMC SPI bus
|
2017-08-26 16:31:31 -07:00 |
|
|
dbc12540da
|
sayma_amc: register RTM CSR regions from CSV
|
2017-08-26 14:48:11 -07:00 |
|
|
54c75d3274
|
sayma_rtm: use CSR infrastructure, generate CSR CSV
|
2017-08-23 17:19:53 -04:00 |
|
|
668450db26
|
sayma_amc: add serwb
|
2017-08-21 18:11:29 -04:00 |
|
|
0459a70cf6
|
sayma_amc: cleanup, fix RTM UART forwarding
|
2017-08-21 16:49:42 -04:00 |
|
|
1f2b373d09
|
sayma_rtm: remove unnecessary serwb_control
|
2017-08-21 16:37:13 -04:00 |
|
|
bfea297279
|
targets: add Sayma RTM
|
2017-08-21 15:58:01 -04:00 |
|
|
53c7f92fdc
|
serwb: add __init__.py and expose submodules
|
2017-08-21 15:57:43 -04:00 |
|
|
dac3a78b75
|
serwb: style, use migen, fix imports
|
2017-08-21 12:35:59 -04:00 |
|
Florent Kermarrec
|
da90a0fa12
|
Add test for Etherbone
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
|
2017-08-21 12:31:49 -04:00 |
|
Florent Kermarrec
|
44dc76e42e
|
Add serial Wishbone bridge
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
|
2017-08-21 12:22:05 -04:00 |
|
|
d6b624dfbe
|
sayma_amc: connect RTM serial and second serial
|
2017-08-20 19:01:55 -04:00 |
|
|
e94d0803e1
|
artiq_flash: fix Sayma load addresses
|
2017-08-20 18:21:36 -04:00 |
|
|
261b6fb42e
|
artiq_flash: fix AMC_DR_LEN
|
2017-08-20 18:20:51 -04:00 |
|
|
9f4c9fc14b
|
artiq_flash: Sayma support
|
2017-08-20 17:23:56 -04:00 |
|
|
bee4902323
|
add Sayma AMC standalone target
|
2017-08-20 11:47:45 -04:00 |
|
|
ac83bfbd8e
|
runtime: add support for targets without SPI flash
|
2017-08-20 11:28:57 -04:00 |
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