forked from M-Labs/artiq
sayma_rtm: drive DAC control signals
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@ -88,6 +88,12 @@ class SaymaRTM(Module):
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platform.request("dac_clk_src_sel").eq(0), # use clk from dac_clk
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]
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self.comb += [
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platform.request("ad9154_rst_n").eq(0),
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platform.request("ad9154_txen", 0).eq(0b11),
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platform.request("ad9154_txen", 1).eq(0b11)
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]
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self.submodules.converter_spi = spi.SPIMaster(platform.request("hmc_spi"))
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csr_devices.append("converter_spi")
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self.comb += platform.request("hmc7043_reset").eq(0)
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