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gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction

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This commit is contained in:
Florent Kermarrec 2017-08-29 16:41:29 +02:00
parent 60ad36e7d6
commit 7d7f6be7ce
1 changed files with 30 additions and 20 deletions
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50
artiq/gateware/serwb/etherbone.py
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@ -667,33 +667,43 @@ class EtherboneWishboneSlave(Module):
)
)
fsm.act("SEND_WRITE",
source.stb.eq(1),
source.eop.eq(1),
source.base_addr[2:].eq(bus.adr),
source.count.eq(1),
source.be.eq(bus.sel),
source.we.eq(1),
source.data.eq(bus.dat_w),
If(source.stb & source.ack,
bus.ack.eq(1),
NextState("IDLE")
If(~self.ready,
NextState("SEND_ERROR")
).Else(
source.stb.eq(1),
source.eop.eq(1),
source.base_addr[2:].eq(bus.adr),
source.count.eq(1),
source.be.eq(bus.sel),
source.we.eq(1),
source.data.eq(bus.dat_w),
If(source.stb & source.ack,
bus.ack.eq(1),
NextState("IDLE")
)
)
)
fsm.act("SEND_READ",
source.stb.eq(1),
source.eop.eq(1),
source.base_addr.eq(0),
source.count.eq(1),
source.be.eq(bus.sel),
source.we.eq(0),
source.data[2:].eq(bus.adr),
If(source.stb & source.ack,
NextState("WAIT_READ")
If(~self.ready,
NextState("SEND_ERROR")
).Else(
source.stb.eq(1),
source.eop.eq(1),
source.base_addr.eq(0),
source.count.eq(1),
source.be.eq(bus.sel),
source.we.eq(0),
source.data[2:].eq(bus.adr),
If(source.stb & source.ack,
NextState("WAIT_READ")
)
)
)
fsm.act("WAIT_READ",
sink.ack.eq(1),
If(sink.stb & sink.we,
If(~self.ready,
NextState("SEND_ERROR")
).Elif(sink.stb & sink.we,
bus.ack.eq(1),
bus.dat_r.eq(sink.data),
NextState("IDLE")