Commit Graph

1340 Commits

Author SHA1 Message Date
1d34c06d79 rtio: detect collision errors 2015-07-29 19:43:35 +08:00
b548d50a2f test/coredevice: use ttl_out for PulseRate (loop is less available) 2015-07-29 19:42:43 +08:00
whitequark
c40ae9dbd3 MiSoC is not built with -fPIC anymore, remove support code for that. 2015-07-29 12:40:46 +03:00
ebbbdcf194 examples/tdr: cleanup 2015-07-28 23:30:26 -06:00
278570faf6 examples: add TDR toy example 2015-07-28 21:36:10 -06:00
90368415a6 ttl: remove timestamp function
The general idea is that functions that work with absolute timestamps exist only in machine units versions, to help prevent floating point losses of precision. Time differences should be computed in machine units and then converted, e.g. mu_to_seconds(t2-t1).

This function would have had problems after ~50 days of running the device.
2015-07-29 11:11:16 +08:00
2640a57af3 test/coredevice: let output() settle longer 2015-07-28 16:20:05 -06:00
5f5227f01f ttl: add timestamp() 2015-07-28 16:20:05 -06:00
e95b66f114 ttl: remove spurious _mu 2015-07-28 16:20:05 -06:00
whitequark
b179430f6b Specify correct llvmlite branch in installation instructions. 2015-07-28 23:43:07 +03:00
67715f0d2e pipistrello: only put serdes on the lower ttls
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
2015-07-28 12:54:31 -06:00
fb339d294e serdes_s6: no need to reset 2015-07-28 12:54:31 -06:00
9dfbf07743 pipistrello: use 4x serdes for rtio ttl
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
2015-07-28 12:54:27 -06:00
8e391e2661 kc705: generate 10MHz clock on GPIO SMA
For SynthNV and input tests.
2015-07-28 18:56:47 +08:00
1809a70f5c Revert "pipistrello: use 4x serdes for rtio ttl"
This reverts commit 8e92cc91f5.

Broken. Will revisit.
2015-07-27 23:39:35 -06:00
f0a7078336 Revert "rtiocrg.c: pipistrello also has pll_reset"
This reverts commit bdee914828.
2015-07-27 22:18:45 -06:00
bdee914828 rtiocrg.c: pipistrello also has pll_reset 2015-07-27 22:14:42 -06:00
e95b06e96d pipistrello: tie unused dds.p low 2015-07-27 21:48:56 -06:00
8e92cc91f5 pipistrello: use 4x serdes for rtio ttl 2015-07-27 21:29:50 -06:00
9ac5bc52d4 rtio: add spartan6 serdes, 4x and 8x 2015-07-27 21:01:15 -06:00
ae3a52c49c runtime: fix KERNELCPU_PAYLOAD_ADDRESS 2015-07-28 02:12:14 +08:00
whitequark
eec4a2d2d2 Update buildsystem to track -fPIC and ranlib removal in MiSoC. 2015-07-27 21:10:46 +03:00
0cd74533ca runtime: more explicit message about startup clock failure 2015-07-28 00:38:38 +08:00
228f7c3d61 manual: update xc3sprog download 2015-07-28 00:38:20 +08:00
7feaca7c7c runtime: allow selecting external clock at startup 2015-07-28 00:19:07 +08:00
09d837e4ba runtime: monitor RTIO clock status 2015-07-28 00:05:24 +08:00
299bc1cb7e kc705: output divided-by-2 RTIO clock 2015-07-27 20:46:44 +08:00
256e99f0d7 kc705: crg cleanup 2015-07-27 20:31:37 +08:00
2a95e866aa kc705: use 8X SERDES RTIO PHY 2015-07-27 20:12:17 +08:00
fe57308e71 runtime: support for RTIO PLL 2015-07-27 20:11:31 +08:00
d7138b25f2 examples/ddb: add device aliases for unittests 2015-07-27 12:22:56 +08:00
b1d58bd4c8 rtio: fix replace/sequence_error when fine_ts_width > 0 2015-07-27 12:22:35 +08:00
959b7a7b46 rtio: resetless -> reset_less 2015-07-27 11:46:56 +08:00
117b361a06 Merge branch 'master' of github.com:m-labs/artiq 2015-07-27 11:42:29 +08:00
3573fd02a6 targets/kc705: add TIG constraints for ISE 2015-07-27 10:58:19 +08:00
fe6a5c42df rtio: remove unused clk_freq argument 2015-07-27 10:57:15 +08:00
5b50f5fe05 rtio/ttl_serdes_7series: use recommended OSERDES T configuration 2015-07-27 10:50:50 +08:00
d3f05e414a runtime: account for RTIO_FINE_TS_WIDTH in time buffers 2015-07-27 10:50:25 +08:00
whitequark
905abd6e27 get-toolchain.sh: be less verbose. 2015-07-27 04:57:13 +03:00
d65d303ac6 pipistrello: remove unused constraint kwarg 2015-07-26 17:39:07 -06:00
f68d5cbd73 rtio: forward rtio domain reset to rio and rio_phy domains 2015-07-27 01:52:47 +08:00
940aa815dd rtio/ttl_serdes: cleanup/rewrite 2015-07-27 01:44:52 +08:00
whitequark
1d9f40833d Update ldscripts with -fPIC support. 2015-07-26 16:16:48 +03:00
whitequark
d252a00b56 Add prebuilt or1k-linux binutils and or1k llvm for travis. 2015-07-26 14:12:48 +03:00
Yann Sionneau
d90dff4ef1 rtio: add SERDES TTL (WIP) 2015-07-26 17:40:34 +08:00
whitequark
cf16da5763 Add a setuptools command to rsync the documentation. 2015-07-26 09:57:05 +03:00
whitequark
163edc02c6 Fix Mock usage in sphinx configuration. 2015-07-26 09:49:39 +03:00
whitequark
95f7be0a88 Update install instructions to reflect that LLVM is always needed. 2015-07-26 09:38:43 +03:00
whitequark
e5acdfe3fd Update manual install instructions. 2015-07-26 09:28:11 +03:00
aba2d3f112 runtime: process essential kernel CPU messages at all time 2015-07-25 16:26:04 +08:00