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pipistrello: use 4x serdes for rtio ttl

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pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
This commit is contained in:
Robert Jördens 2015-07-27 21:29:50 -06:00
parent 8e391e2661
commit 9dfbf07743
1 changed files with 78 additions and 32 deletions
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110
soc/targets/artiq_pipistrello.py
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@ -3,6 +3,8 @@ from fractions import Fraction
from migen.fhdl.std import *
from migen.bank.description import *
from migen.bank import wbgen
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.cdc import MultiReg
from misoclib.com import gpio
from misoclib.soc import mem_decoder
@ -11,46 +13,84 @@ from targets.pipistrello import BaseSoC
from artiq.gateware.soc import AMPSoC
from artiq.gateware import rtio, nist_qc1
from artiq.gateware.rtio.phy import ttl_simple, dds
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds
class _RTIOCRG(Module, AutoCSR):
def __init__(self, platform, clk_freq):
self._clock_sel = CSRStorage()
self.clock_domains.cd_rtio = ClockDomain(reset_less=True)
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
f = Fraction(125*1000*1000, clk_freq)
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
self.clock_domains.cd_rtiox8 = ClockDomain(reset_less=True)
self.rtiox4_stb = Signal()
self.rtiox8_stb = Signal()
rtio_f = 125*1000*1000
f = Fraction(rtio_f, clk_freq)
rtio_internal_clk = Signal()
self.specials += Instance("DCM_CLKGEN",
p_CLKFXDV_DIVIDE=2,
p_CLKFX_DIVIDE=f.denominator,
p_CLKFX_MD_MAX=float(f),
p_CLKFX_MULTIPLY=f.numerator,
p_CLKIN_PERIOD=1e9/clk_freq,
p_SPREAD_SPECTRUM="NONE",
p_STARTUP_WAIT="FALSE",
i_CLKIN=ClockSignal(),
o_CLKFX=rtio_internal_clk,
i_FREEZEDCM=0,
i_RST=ResetSignal())
rtio_external_clk = platform.request("pmt", 2)
# ISE infers constraints for the internal clock
# and propagates them through the BUFGMUX. Adding this:
# platform.add_period_constraint(rtio_external_clk, 8.0)
# seems to confuse it
self.specials += Instance("BUFGMUX",
i_I0=rtio_internal_clk,
i_I1=rtio_external_clk,
i_S=self._clock_sel.storage,
o_O=self.cd_rtio.clk)
rtio_external_clk = Signal()
pmt2 = platform.request("pmt", 2)
dcm_locked = Signal()
rtio_clk = Signal()
pll_locked = Signal()
pll = Signal(3)
pll_fb = Signal()
self.specials += [
Instance("IBUFG", i_I=pmt2, o_O=rtio_external_clk),
Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2,
p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f),
p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq,
p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
i_CLKIN=ClockSignal(), o_CLKFX=rtio_internal_clk,
i_FREEZEDCM=0, i_RST=ResetSignal(), o_LOCKED=dcm_locked),
Instance("BUFGMUX",
i_I0=rtio_internal_clk, i_I1=rtio_external_clk,
i_S=self._clock_sel.storage, o_O=rtio_clk),
Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0,
i_RST=self._pll_reset.storage | ~dcm_locked, i_REL=0,
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=8,
p_CLKFBOUT_PHASE=0., i_CLKINSEL=1,
i_CLKIN1=rtio_clk, i_CLKIN2=0,
p_CLKIN1_PERIOD=1e9/rtio_f, p_CLKIN2_PERIOD=0.,
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_locked,
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=1,
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=2,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=8),
Instance("BUFPLL", p_DIVIDE=8,
i_PLLIN=pll[0], i_GCLK=self.cd_rtio.clk,
i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox8.clk,
o_SERDESSTROBE=self.rtiox8_stb),
Instance("BUFPLL", p_DIVIDE=4,
i_PLLIN=pll[1], i_GCLK=self.cd_rtio.clk,
i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox4.clk,
o_SERDESSTROBE=self.rtiox4_stb),
Instance("BUFG", i_I=pll[2], o_O=self.cd_rtio.clk),
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self._pll_locked.status),
]
# ISE infers correct period constraints for cd_rtio.clk from
# the internal clock. The first two TIGs target just the BUFGMUX.
platform.add_platform_command("""
NET "{int_clk}" TNM_NET = "GRPint_clk";
NET "sys_clk" TNM_NET = "GRPsys_clk";
TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
NET "{ext_clk}" TNM_NET = "GRPext_clk";
TIMESPEC "TSfix_ise1" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
NET "{int_clk}" TNM_NET = "GRPint_clk";
TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
""", int_clk=rtio_internal_clk)
NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
TIMESPEC "TSfix_ise3" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
""", ext_clk=rtio_external_clk, int_clk=rtio_internal_clk,
rtio_clk=self.cd_rtio.clk)
class NIST_QC1(BaseSoC, AMPSoC):
@ -73,6 +113,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
sdram_controller_settings=MiniconSettings(l2_size=64*1024),
with_timer=False, **kwargs)
AMPSoC.__init__(self)
platform.toolchain.bitgen_opt = "-g Binary:Yes -w"
platform.toolchain.ise_commands += """
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
"""
@ -90,16 +131,22 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
platform.request("ttl_h_tx_en").eq(1)
]
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
# RTIO channels
rtio_channels = []
# pmt1 can run on a 8x serdes if pmt0 is not used
for i in range(2):
phy = ttl_simple.Inout(platform.request("pmt", i))
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
ofifo_depth=4))
# ttl2 can run on a 8x serdes if xtrig is not used
for i in range(15):
phy = ttl_simple.Output(platform.request("ttl", i))
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
@ -129,7 +176,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
ififo_depth=4))
# RTIO core
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)