1
0
Fork 0

Compare commits

...

42 Commits

Author SHA1 Message Date
morgan a6b1701de3 cxp downconn: fix aligner not work @ 5 & 6.25Gbps 2024-08-14 17:14:06 +08:00
morgan aa128e1467 cxp downconn fw: change to 40bits 2024-08-14 16:48:51 +08:00
morgan 49d5cad5fd cxp downconn: use 40bits 2024-08-14 16:48:36 +08:00
morgan 17277504f1 cxp downconn: remove unnessary waitimer 2024-08-13 12:34:59 +08:00
morgan a715b66f9d cxp downconn fw: add qpll drg config 2024-08-13 12:05:42 +08:00
morgan 692edeadfc cxp downconn: extend comma_det check period 2024-08-13 11:58:43 +08:00
morgan 6e4ae2e1d1 cxp downconn: add qpll drp 2024-08-13 11:58:29 +08:00
morgan 5ddd2cd730 cxp downconn fw: put drp into mod & add rxcdr_cfg 2024-08-12 17:44:26 +08:00
morgan 5dfef7e457 cxp downconn fw: add drp example 2024-08-12 16:48:20 +08:00
morgan bfc8f065f7 cxp downconn: add gtx drp 2024-08-12 16:48:05 +08:00
morgan 2cd1da81c1 cxp downconn: cleanup & add reason for comma_det 2024-08-12 11:13:05 +08:00
morgan e055a11e1c cxp downconn: cleanup comma detector 2024-08-09 16:52:13 +08:00
morgan 1f8ef6bf96 cxp downconn: use auto aligner
cxp downconn: fix autoaligner checking
2024-08-09 15:37:45 +08:00
morgan 0e69c5d5ba cxp downconn: refactor bruteforce aligner 2024-08-09 15:37:22 +08:00
morgan dbce74d831 cxp downconn: cleanup & use bruteforce aligner 2024-08-09 15:37:22 +08:00
morgan 2aef11143a cxp downconn fw: doc clean up 2024-08-02 12:40:16 +08:00
morgan 77bff39212 cxp downconn fw: add manual alignment test 2024-08-02 12:36:46 +08:00
morgan 160fcc657a cxp downconn: remove bruteforce aligner 2024-08-02 12:36:46 +08:00
morgan bf1fd2d79b cxp downconn: add manual alignment & rxrestart 2024-08-02 12:36:46 +08:00
morgan 452c3cee64 cxp downconn fw: add CXP datarate update printout 2024-08-01 17:38:12 +08:00
morgan 4436dc930e cxp downconn fw: add qpll linerate change 2024-08-01 12:33:22 +08:00
morgan 5a40422f1d cxp downconn: fix tx reset & cleanup 2024-08-01 11:21:36 +08:00
morgan e0369d2eb2 cxp downconn fw: add DRP for linerate 2024-07-31 16:10:25 +08:00
morgan 1e87428c68 cxp downconn: add DRP for tx/rx divider 2024-07-31 16:10:06 +08:00
morgan 0e4fb4cbfe cxp downconn fw: add QPLL setup 2024-07-29 17:23:00 +08:00
morgan ccd3e6618a cxp downconn: replace QPLL with CPLL
cxp downconn: add QPLL with its reset CSR
cxp downconn: set QPLL as CLK source for GTX
cxp downconn: remove PLL_reset signal from tx_init to prevent race
condition
cxp downconn: rename cxp_gtx to GTX
2024-07-29 17:22:32 +08:00
morgan 563e06ca8d cxp upconn: disable debug sma & pmod output 2024-07-29 17:20:10 +08:00
morgan 57d6e9a669 cxp downconn fw: update csr function name 2024-07-26 17:36:29 +08:00
morgan 1f0154d5b2 cxp: remove all cxp downconn interface 2024-07-26 17:36:16 +08:00
morgan a41e78d3d3 cxp downconn: add csr interface here 2024-07-26 17:36:06 +08:00
morgan 52f77a6331 cxp downconn fw: remove data[4:8] 2024-07-26 17:01:54 +08:00
morgan 1a210a010a cxp: remove data[4:8] 2024-07-26 17:01:26 +08:00
morgan 398eb135c7 cxp downconn: push IDLE word to buf b4 tx&rx init 2024-07-26 16:26:08 +08:00
morgan 865434763d cxp downconn: fix bruteforcealigner 2024-07-26 16:24:18 +08:00
morgan 4ba1c5ef2e cxp downconn fw: add idle data 2024-07-26 15:24:59 +08:00
morgan faef1d2dff cxp downconn: add interface for buildin aligner 2024-07-26 15:24:58 +08:00
morgan 20e388d043 cxp downconn: explore cpll & txusrclk_pll divider 2024-07-25 17:39:11 +08:00
morgan 6c53447808 cxp downconn firmware: init
cxp down fw: cleanup
2024-07-23 17:43:06 +08:00
morgan 14aa81c8a2 cxp upconn firmware: init 2024-07-23 17:09:33 +08:00
morgan 82af01350f cxp: add upconn, downconn & crc
cxp: add crc32 for cxp
cxp: add upconn & downconn
2024-07-23 17:09:22 +08:00
morgan 1f033d605c cxp upconn: add low speed serial
cxp upconn: add low speed serial
cxp upconn: add pll for bitrate2x mode
cxp upconn: add tx_fifos & idle with encoder
cxp upconn: add priority packet that send in word/char boundary
2024-07-23 17:08:33 +08:00
morgan 7d5e3c1ef9 cxp downconn: add high speed serial
cxp downconn: add bruteforcephase aligner
cxp downconn: add gtx with mmcm for TXUSRCLK freq requirement
cxp downconn: add loopback mode parameter for testing
2024-07-23 17:08:33 +08:00
6 changed files with 1890 additions and 0 deletions

74
src/gateware/cxp.py Normal file
View File

@ -0,0 +1,74 @@
from migen import *
from misoc.interconnect.csr import *
from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
from cxp_downconn import CXP_DownConn
from cxp_upconn import CXP_UpConn
class CXP(Module, AutoCSR):
def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
self.submodules.crc = CXP_CRC(8)
# FIFOs with transmission priority
# 0: Trigger packet
# 1: IO acknowledgment for trigger packet
# 2: All other packets
self.submodules.upconn = CXP_UpConn(debug_sma, sys_clk_freq, pmod_pads)
self.submodules.downconn = CXP_DownConn(refclk, pads, sys_clk_freq, debug_sma, pmod_pads)
class CXP_CRC(Module, AutoCSR):
width = 32
polynom = 0x04C11DB7
seed = 2**width-1
def __init__(self, data_width):
self.d = Signal(data_width)
self.stb = Signal()
self.reset = Signal()
self.val = Signal(self.width, reset=self.seed)
self.data = CSR(data_width)
self.en = CSR()
self.value = CSRStatus(self.width)
self.processed = CSRStatus(self.width)
# # #
self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
self.sync += [
self.val.eq(self.engine.next),
If(self.stb,
self.engine.data.eq(self.d),
If(self.reset,
self.engine.last.eq(self.seed),
# clear reset bit
self.reset.eq(0),
).Else(
self.engine.last.eq(self.val),
)
),
]
# DEBUG: remove those csr
# TODO: do char bit reverse outside of this submodule
p0 = Signal(8)
p1 = Signal(8)
p2 = Signal(8)
p3 = Signal(8)
self.comb += [
p3.eq(self.engine.next[:8][::-1]),
p2.eq(self.engine.next[8:16][::-1]),
p1.eq(self.engine.next[16:24][::-1]),
p0.eq(self.engine.next[24:32][::-1]),
]
self.sync += [
self.d.eq(self.data.r),
self.stb.eq(self.data.re),
If(self.en.re, self.reset.eq(1)),
self.value.status.eq(self.engine.next),
self.processed.status.eq(Cat(p3, p2, p1, p0)),
]

View File

@ -0,0 +1,834 @@
from migen import *
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.cores.code_8b10b import Encoder, Decoder
from misoc.interconnect.csr import *
from artiq.gateware.drtio.transceiver.gtx_7series_init import *
from functools import reduce
from operator import add
class CXP_DownConn(Module, AutoCSR):
def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
self.rx_start_init = CSRStorage()
self.rx_restart = CSR()
self.tx_start_init = CSRStorage()
self.tx_restart = CSR()
self.txenable = CSRStorage()
self.txinit_phaligndone = CSRStatus()
self.rxinit_phaligndone = CSRStatus()
self.rx_ready = CSRStatus()
self.qpll_reset = CSR()
self.qpll_locked = CSRStatus()
# # #
self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
# single & master tx_mode can lock with rx in loopback
self.submodules.gtx = gtx = GTX(self.qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
# TEST: txusrclk alignment
# 1) use GTREFCLK with TXSYSCLKSEL = 0b10 -> still inconsistant
# 2) tie qpllPDEN with ~qpll.reset, -> inconsistant
# 3) seems like tx_init gtxXreset fall too soon (cplllock hold hi too long) <--- this a cross clk domain issue :<
self.sync += [
# PLL
qpll.reset.eq(self.qpll_reset.re),
self.qpll_locked.status.eq(qpll.lock),
# GTX
self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
self.rx_ready.status.eq(gtx.rx_ready),
gtx.txenable.eq(self.txenable.storage[0]),
gtx.tx_restart.eq(self.tx_restart.re),
gtx.rx_restart.eq(self.rx_restart.re),
gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
]
# GTX Channels DRP
self.tx_div = CSRStorage(3)
self.rx_div = CSRStorage(3)
self.gtx_daddr = CSRStorage(9)
self.gtx_dread = CSR()
self.gtx_din_stb = CSR()
self.gtx_din = CSRStorage(16)
self.gtx_dout = CSRStatus(16)
self.gtx_dready = CSR()
self.comb += gtx.dclk.eq(ClockSignal("sys"))
self.sync += [
gtx.tx_rate.eq(self.tx_div.storage),
gtx.rx_rate.eq(self.rx_div.storage),
gtx.den.eq(0),
gtx.dwen.eq(0),
If(self.gtx_dread.re,
gtx.den.eq(1),
gtx.daddr.eq(self.gtx_daddr.storage),
).Elif(self.gtx_din_stb.re,
gtx.den.eq(1),
gtx.dwen.eq(1),
gtx.daddr.eq(self.gtx_daddr.storage),
gtx.din.eq(self.gtx_din.storage),
),
If(gtx.dready,
self.gtx_dready.w.eq(1),
self.gtx_dout.status.eq(gtx.dout),
),
If(self.gtx_dready.re,
self.gtx_dready.w.eq(0),
),
]
# QPLL DRP
self.qpll_daddr = CSRStorage(8)
self.qpll_dread = CSR()
self.qpll_din_stb = CSR()
self.qpll_din = CSRStorage(16)
self.qpll_dout = CSRStatus(16)
self.qpll_dready = CSR()
self.comb += qpll.dclk.eq(ClockSignal("sys"))
self.sync += [
qpll.den.eq(0),
qpll.dwen.eq(0),
If(self.qpll_dread.re,
qpll.den.eq(1),
qpll.daddr.eq(self.qpll_daddr.storage),
).Elif(self.qpll_din_stb.re,
qpll.den.eq(1),
qpll.dwen.eq(1),
qpll.daddr.eq(self.qpll_daddr.storage),
qpll.din.eq(self.qpll_din.storage),
),
If(qpll.dready,
self.qpll_dready.w.eq(1),
self.qpll_dout.status.eq(qpll.dout),
),
If(self.qpll_dready.re,
self.qpll_dready.w.eq(0),
),
]
# DEBUG: txusrclk PLL DRG
self.txpll_reset = CSRStorage()
self.pll_daddr = CSRStorage(7)
self.pll_dclk = CSRStorage()
self.pll_den = CSRStorage()
self.pll_din = CSRStorage(16)
self.pll_dwen = CSRStorage()
self.txpll_locked = CSRStatus()
self.pll_dout = CSRStatus(16)
self.pll_dready = CSRStatus()
self.comb += [
gtx.txpll_reset.eq(self.txpll_reset.storage),
gtx.pll_daddr.eq(self.pll_daddr.storage),
gtx.pll_dclk.eq(self.pll_dclk.storage),
gtx.pll_den.eq(self.pll_den.storage),
gtx.pll_din.eq(self.pll_din.storage),
gtx.pll_dwen.eq(self.pll_dwen.storage),
self.txpll_locked.status.eq(gtx.txpll_locked),
self.pll_dout.status.eq(gtx.pll_dout),
self.pll_dready.status.eq(gtx.pll_dready),
]
# DEBUG:loopback
self.loopback_mode = CSRStorage(3)
self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
# DEBUG: IO SMA & PMOD
self.specials += [
Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
# pmod 0-7 pin
Instance("OBUF", i_I=gtx.comma_det.word_aligned, o_O=pmod_pads[0]),
Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[1]),
Instance("OBUF", i_I=gtx.comma_det.aligner_en_rxclk, o_O=pmod_pads[2]),
Instance("OBUF", i_I=gtx.comma_det.check_reset, o_O=pmod_pads[3]),
Instance("OBUF", i_I=gtx.comma_det.comma_aligned, o_O=pmod_pads[4]),
Instance("OBUF", i_I=gtx.comma_det.comma_seen, o_O=pmod_pads[5]),
Instance("OBUF", i_I=gtx.comma_det.has_error, o_O=pmod_pads[6]),
Instance("OBUF", i_I=gtx.comma_det.ready, o_O=pmod_pads[7]),
# Instance("OBUF", i_I=gtx.dclk, o_O=pmod_pads[0]),
# Instance("OBUF", i_I=gtx.den, o_O=pmod_pads[1]),
# Instance("OBUF", i_I=gtx.dwen, o_O=pmod_pads[2]),
# Instance("OBUF", i_I=gtx.dready, o_O=pmod_pads[3]),
]
# DEBUG: datain
self.data_0 = CSRStorage(8)
self.data_1 = CSRStorage(8)
self.data_2 = CSRStorage(8)
self.data_3 = CSRStorage(8)
self.control_bit_0 = CSRStorage()
self.control_bit_1 = CSRStorage()
self.control_bit_2 = CSRStorage()
self.control_bit_3 = CSRStorage()
self.encoded_0 = CSRStatus(10)
self.encoded_1 = CSRStatus(10)
self.rxdata_0 = CSRStatus(10)
self.rxdata_1 = CSRStatus(10)
self.decoded_data_0 = CSRStatus(8)
self.decoded_data_1 = CSRStatus(8)
self.decoded_k_0 = CSRStatus()
self.decoded_k_1 = CSRStatus()
self.sync.cxp_gtx_tx += [
self.gtx.encoder.d[0].eq(0xBC),
self.gtx.encoder.k[0].eq(1),
self.gtx.encoder.d[1].eq(0x3C),
self.gtx.encoder.k[1].eq(1),
self.gtx.encoder.d[2].eq(0x3C),
self.gtx.encoder.k[2].eq(1),
self.gtx.encoder.d[3].eq(0xB5),
self.gtx.encoder.k[3].eq(0),
self.encoded_0.status.eq(self.gtx.encoder.output[0]),
self.encoded_1.status.eq(self.gtx.encoder.output[1]),
]
# keep it odd, so it will show data[n] where n is odd
stb_timer = Signal(reset=10, max=11)
self.sync.cxp_gtx_rx += [
If(stb_timer == 0,
self.rxdata_0.status.eq(self.gtx.decoders[0].input),
self.decoded_data_0.status.eq(self.gtx.decoders[0].d),
self.decoded_k_0.status.eq(self.gtx.decoders[0].k),
self.rxdata_1.status.eq(self.gtx.decoders[1].input),
self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
stb_timer.eq(stb_timer.reset),
).Else(
stb_timer.eq(stb_timer - 1),
)
]
# The TX phase alignment will fail with a wrong TXUSRCLK frequency
# NOTE: No need to connect cxp_gtx_tx, we don't use tx anyway (just for loopback)
# TODO: Connect slave cxp_gtx_rx clock tgt
# checkout channel interfaces & drtio_gtx
# checkout GTPTXPhaseAlignement for inspiration
class QPLL(Module):
def __init__(self, refclk, sys_clk_freq):
self.clk = Signal()
self.refclk = Signal()
self.lock = Signal()
self.reset = Signal()
# Dynamic Reconfiguration Ports
self.daddr = Signal(8)
self.dclk = Signal()
self.den = Signal()
self.dwen = Signal()
self.din = Signal(16)
self.dout = Signal(16)
self.dready = Signal()
# # #
# WARNING: VCO cannot do 12.5GHz on ZC706
# VCO freq = sys*qpll_fbdiv
# PLL output = VCO/2
qpll_fbdiv = 0b0100100000 # 80 div
qpll_fbdiv_ratio = 1
fbdiv_real = 80
refclk_div = 1
self.Xxout_div = 8
# qpll_fbdiv = 0b0101110000 # 100 div
# qpll_fbdiv_ratio = 1
# fbdiv_real = 100
# refclk_div = 2
# self.Xxout_div = 2
self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
self.specials += [
Instance("GTXE2_COMMON",
i_QPLLREFCLKSEL=0b001,
i_GTREFCLK0=refclk,
i_QPLLPD=0,
i_QPLLRESET=self.reset,
i_QPLLLOCKEN=1,
o_QPLLLOCK=self.lock,
o_QPLLOUTCLK=self.clk,
o_QPLLOUTREFCLK=self.refclk,
# See UG476 (v1.12.1) Table 2-16
p_QPLL_FBDIV=qpll_fbdiv,
p_QPLL_FBDIV_RATIO=qpll_fbdiv_ratio,
p_QPLL_REFCLK_DIV=refclk_div,
# From 7 Series FPGAs Transceivers Wizard
p_BIAS_CFG=0x0000040000001000,
p_COMMON_CFG=0x00000000,
p_QPLL_CFG=0x0680181,
p_QPLL_CLKOUT_CFG=0b0000,
p_QPLL_COARSE_FREQ_OVRD=0b010000,
p_QPLL_COARSE_FREQ_OVRD_EN=0b0,
p_QPLL_CP=0b0000011111,
p_QPLL_CP_MONITOR_EN=0b0,
p_QPLL_DMONITOR_SEL=0b0,
p_QPLL_FBDIV_MONITOR_EN= 0b0,
p_QPLL_INIT_CFG=0x000006,
p_QPLL_LOCK_CFG=0x21E8,
p_QPLL_LPF=0b1111,
# Reserved, values cannot be modified
i_BGBYPASSB=0b1,
i_BGMONITORENB=0b1,
i_BGPDB=0b1,
i_BGRCALOVRD=0b11111,
i_RCALENB=0b1,
i_QPLLRSVD1=0b0,
i_QPLLRSVD2=0b11111,
# Dynamic Reconfiguration Ports
i_DRPADDR=self.daddr,
i_DRPCLK=self.dclk,
i_DRPEN=self.den,
i_DRPWE=self.dwen,
i_DRPDI=self.din,
o_DRPDO=self.dout,
o_DRPRDY=self.dready,
)
]
# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
# compared to the usual 8b10b binary representation.
class Comma_Detector(Module):
def __init__(self, comma, check_period=1_000_000):
self.data = Signal(20)
self.word_aligned = Signal()
self.aligner_en_rxclk = Signal()
self.ready = Signal()
self.restart = Signal()
# # #
# The built-in RXBYTEISALIGNED can be falsely asserted at linerate higher than 5Gbps
# - UG476 (v1.12.1) p.228
# The validity of data & comma are checked externally
check_counter = Signal(reset=check_period-1, max=check_period)
# check = Signal()
self.sync += [
self.restart.eq(0),
# check.eq(0),
# check_reset.i.eq(0),
If(~self.ready,
If(check_counter == 0,
check_counter.eq(check_counter.reset),
# check.eq(1),
self.restart.eq(1),
# check_reset.i.eq(1),
).Else(
check_counter.eq(check_counter - 1),
)
)
]
# WIP:
comma_n = ~comma & 0b1111111111
has_error = Signal()
comma_aligned = Signal()
comma_seen = Signal()
error_seen = Signal()
one_counts = Signal(max=11)
counter_period = 5000
counter = Signal(reset=counter_period-1, max=counter_period)
check_reset = Signal()
check = Signal()
self.sync.cxp_gtx_rx += [
check.eq(0),
If(counter == 0,
counter.eq(counter.reset),
check.eq(1),
).Else(
counter.eq(counter - 1),
),
has_error.eq(0),
one_counts.eq(reduce(add, [self.data[i] for i in range(10, 20)])),
If((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
has_error.eq(1)
),
comma_aligned.eq(0),
If((self.data[:10] == comma) | (self.data[:10] == comma_n),
comma_aligned.eq(1)
),
# signal that need to be manually cleared
If(check_reset,
comma_seen.eq(0),
).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
comma_seen.eq(1)
),
one_counts.eq(reduce(add, [self.data[i] for i in range(10, 20)])),
If(check_reset,
error_seen.eq(0),
).Elif((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
error_seen.eq(1),
),
]
# DEBUG: expose signal
self.check_reset = Signal()
self.comma_aligned = Signal()
self.comma_seen = Signal()
self.has_error = Signal()
self.error_seen = Signal()
self.comb +=[
self.check_reset.eq(check_reset),
self.comma_aligned.eq(comma_aligned),
self.comma_seen.eq(comma_seen),
self.has_error.eq(has_error),
self.error_seen.eq(error_seen),
]
self.submodules.rxfsm = rxfsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="ALIGNING"))
# the data from gtxe2 is delayed and checking at the output may not reflect the alignment inside the aligner
# thus, failing to alignment on high linerate >5Gbps is common due to the aligner_en being asserted longer than necessary and lead to a lose of lock
# a timer is used to wait till the "aligned" data to arrive and do a system check like the datasheet suggested
self.submodules.timer = timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(5000))
rxfsm.act("ALIGNING",
self.aligner_en_rxclk.eq(1),
If(self.word_aligned,
check_reset.eq(1),
NextState("WAIT_ALIGNED_DATA"),
)
)
rxfsm.act("WAIT_ALIGNED_DATA",
timer.wait.eq(1),
If(timer.done,
check_reset.eq(1),
NextState("CHECKING"),
)
)
rxfsm.act("CHECKING",
If(check,
check_reset.eq(1),
If(comma_seen & (~error_seen),
NextState("READY"),
).Else(
NextState("ALIGNING")
)
)
)
ready = Signal()
self.specials += MultiReg(ready, self.ready)
rxfsm.act("READY",
ready.eq(1),
If(check,
check_reset.eq(1),
If(~(comma_seen & (~error_seen)),
NextState("ALIGNING"),
)
)
)
class GTX(Module):
# Settings:
# * GTX reference clock @ 125MHz
# * GTX data width = 20
# * GTX PLL frequency @ 3.125GHz
# * GTX line rate (TX & RX) @ 3.125Gb/s
# * GTX TX/RX USRCLK @ PLL/datawidth = 156MHz
def __init__(self, qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
assert tx_mode in ["single", "master", "slave"]
assert rx_mode in ["single", "master", "slave"]
# linerate = USRCLK * datawidth
pll_fbout_mult = 8
txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq
self.tx_restart = Signal()
self.rx_restart = Signal()
self.loopback_mode = Signal(3)
self.txenable = Signal()
self.rx_ready = Signal()
self.tx_rate = Signal(3)
self.rx_rate = Signal(3)
# Dynamic Reconfiguration Ports
self.daddr = Signal(9)
self.dclk = Signal()
self.den = Signal()
self.dwen = Signal()
self.din = Signal(16)
self.dout = Signal(16)
self.dready = Signal()
self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(4, True))
self.submodules.decoders = [ClockDomainsRenamer("cxp_gtx_rx")(
(Decoder(True))) for _ in range(4)]
# transceiver direct clock outputs
# useful to specify clock constraints in a way palatable to Vivado
self.txoutclk = Signal()
self.rxoutclk = Signal()
# # #
# TX generates cxp_tx clock, init must be in system domain
# FIXME: 500e6 is used to fix Xx reset by holding gtxXxreset for a couple cycle more
self.submodules.tx_init = tx_init = GTXInit(500e6, False, mode=tx_mode)
self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
# RX receives restart commands from txusrclk domain
# self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(500e6, True, mode=rx_mode))
self.comb += [
tx_init.cplllock.eq(qpll.lock),
rx_init.cplllock.eq(qpll.lock)
]
txdata = Signal(40)
rxdata = Signal(40)
word_aligned = Signal()
comma_aligner_en = Signal()
# Note: the following parameters were set after consulting AR45360
self.specials += \
Instance("GTXE2_CHANNEL",
# PMA Attributes
p_PMA_RSV=0x00018480,
p_PMA_RSV2=0x2050, # PMA_RSV2[5] = 0: Eye scan feature disabled
p_PMA_RSV3=0,
p_PMA_RSV4=1, # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
p_RX_BIAS_CFG=0b000000000100,
p_RX_OS_CFG=0b0000010000000,
p_RX_CLK25_DIV=5,
p_TX_CLK25_DIV=5,
# Power-Down Attributes
p_PD_TRANS_TIME_FROM_P2=0x3c,
p_PD_TRANS_TIME_NONE_P2=0x3c,
p_PD_TRANS_TIME_TO_P2=0x64,
i_CPLLPD=1,
# Dynamic Tx/Rx divider
i_TXRATE=self.tx_rate,
i_RXRATE=self.rx_rate,
# QPLL
i_QPLLCLK=qpll.clk,
i_QPLLREFCLK=qpll.refclk,
p_RXOUT_DIV=qpll.Xxout_div,
p_TXOUT_DIV=qpll.Xxout_div,
i_RXSYSCLKSEL=0b11, # use QPLL & QPLL's REFCLK
i_TXSYSCLKSEL=0b11, # use QPLL & CPLL's REFCLK
# TX clock
p_TXBUF_EN="FALSE",
p_TX_XCLK_SEL="TXUSR",
o_TXOUTCLK=self.txoutclk,
# i_TXSYSCLKSEL=0b00,
i_TXOUTCLKSEL=0b11,
# TX Startup/Reset
i_TXPHDLYRESET=0,
i_TXDLYBYPASS=0,
i_TXPHALIGNEN=1 if tx_mode != "single" else 0,
i_GTTXRESET=tx_init.gtXxreset,
o_TXRESETDONE=tx_init.Xxresetdone,
i_TXDLYSRESET=tx_init.Xxdlysreset,
o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
i_TXPHINIT=tx_init.txphinit if tx_mode != "single" else 0,
o_TXPHINITDONE=tx_init.txphinitdone if tx_mode != "single" else Signal(),
i_TXPHALIGN=tx_init.Xxphalign if tx_mode != "single" else 0,
i_TXDLYEN=tx_init.Xxdlyen if tx_mode != "single" else 0,
o_TXPHALIGNDONE=tx_init.Xxphaligndone,
i_TXUSERRDY=tx_init.Xxuserrdy,
p_TXPMARESET_TIME=1,
p_TXPCSRESET_TIME=1,
i_TXINHIBIT=~self.txenable,
# TX data
p_TX_DATA_WIDTH=40,
p_TX_INT_DATAWIDTH=1,
i_TXCHARDISPMODE=Cat(txdata[9], txdata[19], txdata[29], txdata[39]),
i_TXCHARDISPVAL=Cat(txdata[8], txdata[18], txdata[28], txdata[38]),
i_TXDATA=Cat(txdata[:8], txdata[10:18], txdata[20:28], txdata[30:38]),
i_TXUSRCLK=ClockSignal("cxp_gtx_tx"),
i_TXUSRCLK2=ClockSignal("cxp_gtx_tx"),
# TX electrical
i_TXBUFDIFFCTRL=0b100,
i_TXDIFFCTRL=0b1000,
# RX Startup/Reset
i_RXPHDLYRESET=0,
i_RXDLYBYPASS=0,
i_RXPHALIGNEN=1 if rx_mode != "single" else 0,
i_GTRXRESET=rx_init.gtXxreset,
o_RXRESETDONE=rx_init.Xxresetdone,
i_RXDLYSRESET=rx_init.Xxdlysreset,
o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
i_RXPHALIGN=rx_init.Xxphalign if rx_mode != "single" else 0,
i_RXDLYEN=rx_init.Xxdlyen if rx_mode != "single" else 0,
o_RXPHALIGNDONE=rx_init.Xxphaligndone,
i_RXUSERRDY=rx_init.Xxuserrdy,
p_RXPMARESET_TIME=1,
p_RXPCSRESET_TIME=1,
# RX AFE
p_RX_DFE_XYD_CFG=0,
p_RX_CM_SEL=0b11, # RX_CM_SEL = 0b11: Common mode is programmable
p_RX_CM_TRIM=0b010, # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
i_RXDFEXYDEN=1,
i_RXDFEXYDHOLD=0,
i_RXDFEXYDOVRDEN=0,
i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled for non scramble data
p_RX_DFE_GAIN_CFG=0x0207EA,
p_RX_DFE_VP_CFG=0b00011111100000011,
p_RX_DFE_UT_CFG=0b10001000000000000,
p_RX_DFE_KL_CFG=0b0000011111110,
p_RX_DFE_KL_CFG2=0x3788140A,
p_RX_DFE_H2_CFG=0b000110000000,
p_RX_DFE_H3_CFG=0b000110000000,
p_RX_DFE_H4_CFG=0b00011100000,
p_RX_DFE_H5_CFG=0b00011100000,
p_RX_DFE_LPM_CFG=0x0904, # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
# = 0x0104: linerate > 6.6Gb/s
# RX clock
i_RXDDIEN=1,
# i_RXSYSCLKSEL=0b00,
i_RXOUTCLKSEL=0b010,
o_RXOUTCLK=self.rxoutclk,
i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
i_RXUSRCLK2=ClockSignal("cxp_gtx_rx"),
# RX Clock Correction Attributes
p_CLK_CORRECT_USE="FALSE",
p_CLK_COR_SEQ_1_1=0b0100000000,
p_CLK_COR_SEQ_2_1=0b0100000000,
p_CLK_COR_SEQ_1_ENABLE=0b1111,
p_CLK_COR_SEQ_2_ENABLE=0b1111,
# RX data
p_RX_DATA_WIDTH=40,
p_RX_INT_DATAWIDTH=1,
o_RXDISPERR=Cat(rxdata[9], rxdata[19], rxdata[29], rxdata[39]),
o_RXCHARISK=Cat(rxdata[8], rxdata[18], rxdata[28], rxdata[38]),
o_RXDATA=Cat(rxdata[:8], rxdata[10:18], rxdata[20:28], rxdata[30:38]),
# RX Byte and Word Alignment Attributes
p_ALIGN_COMMA_DOUBLE="FALSE",
p_ALIGN_COMMA_ENABLE=0b1111111111,
p_ALIGN_COMMA_WORD=4, # align comma to rxdata[:10] only
p_ALIGN_MCOMMA_DET="TRUE",
p_ALIGN_MCOMMA_VALUE=0b1010000011,
p_ALIGN_PCOMMA_DET="TRUE",
p_ALIGN_PCOMMA_VALUE=0b0101111100,
p_SHOW_REALIGN_COMMA="TRUE",
p_RXSLIDE_AUTO_WAIT=7,
p_RXSLIDE_MODE="OFF",
p_RX_SIG_VALID_DLY=10,
i_RXPCOMMAALIGNEN=comma_aligner_en,
i_RXMCOMMAALIGNEN=comma_aligner_en,
i_RXCOMMADETEN=1,
i_RXSLIDE=0,
o_RXBYTEISALIGNED=word_aligned,
# RX 8B/10B Decoder Attributes
p_RX_DISPERR_SEQ_MATCH="FALSE",
p_DEC_MCOMMA_DETECT="TRUE",
p_DEC_PCOMMA_DETECT="TRUE",
p_DEC_VALID_COMMA_ONLY="FALSE",
# RX Buffer Attributes
p_RXBUF_ADDR_MODE="FAST",
p_RXBUF_EIDLE_HI_CNT=0b1000,
p_RXBUF_EIDLE_LO_CNT=0b0000,
p_RXBUF_EN="FALSE",
p_RX_BUFFER_CFG=0b000000,
p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
p_RXBUF_RESET_ON_EIDLE="FALSE", # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
p_RXBUFRESET_TIME=0b00001,
p_RXBUF_THRESH_OVFLW=61,
p_RXBUF_THRESH_OVRD="FALSE",
p_RXBUF_THRESH_UNDFLW=4,
p_RXDLY_CFG=0x001F,
p_RXDLY_LCFG=0x030,
p_RXDLY_TAP_CFG=0x0000,
p_RXPH_CFG=0xC00002,
p_RXPHDLY_CFG=0x084020,
p_RXPH_MONITOR_SEL=0b00000,
p_RX_XCLK_SEL="RXUSR",
p_RX_DDI_SEL=0b000000,
p_RX_DEFER_RESET_BUF_EN="TRUE",
# CDR Attributes
p_RXCDR_CFG=0x03_0000_23FF_1040_0020, # DFE @ <= 6.6Gb/s, 8B/10B encoded data, CDR setting < +/- 200ppm
# (See UG476 (v1.12.1), p.205)
p_RXCDR_FR_RESET_ON_EIDLE=0b0,
p_RXCDR_HOLD_DURING_EIDLE=0b0,
p_RXCDR_PH_RESET_ON_EIDLE=0b0,
p_RXCDR_LOCK_CFG=0b010101,
# Pads
i_GTXRXP=pads.rxp,
i_GTXRXN=pads.rxn,
o_GTXTXP=pads.txp,
o_GTXTXN=pads.txn,
# Dynamic Reconfiguration Ports
p_IS_DRPCLK_INVERTED=0b0,
i_DRPADDR=self.daddr,
i_DRPCLK=self.dclk,
i_DRPEN=self.den,
i_DRPWE=self.dwen,
i_DRPDI=self.din,
o_DRPDO=self.dout,
o_DRPRDY=self.dready,
# ! loopback for debugging
i_LOOPBACK = self.loopback_mode,
p_TX_LOOPBACK_DRIVE_HIZ = "FALSE",
p_RXPRBS_ERR_LOOPBACK = 0b0,
# Other parameters
p_PCS_RSVD_ATTR=(
(tx_mode != "single") << 1 | # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
# = 1: TX Manual Mode
(rx_mode != "single") << 2 | # [2] = 0: RX Single Lane Auto Mode
# = 1: RX Manual Mode
0 << 8 # [8] = 0: OOB is disabled
),
i_RXELECIDLEMODE=0b11, # RXELECIDLEMODE = 0b11: OOB is disabled
p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
p_ES_EYE_SCAN_EN="TRUE", # Must be TRUE for GTX
)
# TX clocking
# A PLL is used to generate the correct frequency for TXUSRCLK (UG476 Equation 3-1)
self.clock_domains.cd_cxp_gtx_tx = ClockDomain()
txpll_fb_clk = Signal()
txoutclk_buf = Signal()
txpll_clkout = Signal()
self.txpll_reset = Signal()
self.pll_daddr = Signal(7)
self.pll_dclk = Signal()
self.pll_den = Signal()
self.pll_din = Signal(16)
self.pll_dwen = Signal()
self.txpll_locked = Signal()
self.pll_dout = Signal(16)
self.pll_dready = Signal()
self.specials += [
Instance("PLLE2_ADV",
p_BANDWIDTH="HIGH",
o_LOCKED=self.txpll_locked,
i_RST=self.txpll_reset,
p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
i_CLKIN1=txoutclk_buf,
# VCO @ 1.25GHz
p_CLKFBOUT_MULT=pll_fbout_mult, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk,
# frequency = linerate/40
p_CLKOUT0_DIVIDE=txusr_pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
# Dynamic Reconfiguration Ports
i_DADDR = self.pll_daddr,
i_DCLK = self.pll_dclk,
i_DEN = self.pll_den,
i_DI = self.pll_din,
i_DWE = self.pll_dwen,
o_DO = self.pll_dout,
o_DRDY = self.pll_dready,
),
Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_buf),
Instance("BUFG", i_I=txpll_clkout, o_O=self.cd_cxp_gtx_tx.clk),
AsyncResetSynchronizer(self.cd_cxp_gtx_tx, ~self.txpll_locked & ~tx_init.done)
]
# RX clocking
# the CDR matches the required frequency for RXUSRCLK, no need for PLL
self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
self.specials += [
Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
]
self.comb += [
txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1], self.encoder.output[2], self.encoder.output[3])),
self.decoders[0].input.eq(rxdata[:10]),
self.decoders[1].input.eq(rxdata[10:20]),
self.decoders[2].input.eq(rxdata[20:30]),
self.decoders[3].input.eq(rxdata[30:]),
]
self.submodules.comma_det = comma_det = Comma_Detector(0b0101111100)
self.comb += [
comma_det.data.eq(rxdata),
comma_det.word_aligned.eq(word_aligned),
comma_aligner_en.eq(comma_det.aligner_en_rxclk),
self.rx_ready.eq(comma_det.ready),
rx_init.restart.eq(self.rx_restart | comma_det.restart),
tx_init.restart.eq(self.tx_restart),
]

279
src/gateware/cxp_upconn.py Normal file
View File

@ -0,0 +1,279 @@
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.coding import PriorityEncoder
from misoc.cores.code_8b10b import SingleEncoder
from misoc.interconnect import stream
from misoc.interconnect.csr import *
class CXP_UpConn(Module, AutoCSR):
nfifos = 3
def __init__(self, pads, sys_clk_freq, pmod, fifo_depth=32):
self.clock_domains.cd_cxp_upconn = ClockDomain()
self.clk_reset = CSRStorage(reset=1)
self.bitrate2x_enable = CSRStorage()
self.tx_enable = CSRStorage()
# # #
pll_locked = Signal()
pll_fb_clk = Signal()
pll_cxpclk = Signal()
pll_cxpclk2x = Signal()
self.specials += [
Instance("PLLE2_ADV",
p_BANDWIDTH="HIGH",
o_LOCKED=pll_locked,
i_RST=ResetSignal("sys"),
p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
i_CLKIN1=ClockSignal("sys"),
# VCO @ 1.25GHz
p_CLKFBOUT_MULT=1.25e9/sys_clk_freq, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=pll_fb_clk, o_CLKFBOUT=pll_fb_clk,
# 20.83MHz (48ns)
p_CLKOUT0_DIVIDE=60, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_cxpclk,
# 41.66MHz (24ns) for downconnection over 6.25Gpbs
p_CLKOUT1_DIVIDE=30, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_cxpclk2x,
),
Instance("BUFGMUX",
i_I0=pll_cxpclk,
i_I1=pll_cxpclk2x,
i_S=self.bitrate2x_enable.storage,
o_O=self.cd_cxp_upconn.clk
),
AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
]
self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
self.submodules.tx_fifos = TxFIFOs(self.nfifos, fifo_depth)
self.submodules.tx_idle = TxIdle()
o = Signal()
tx_en = Signal()
tx_bitcount = Signal(max=10)
tx_wordcount = Signal(max=4)
tx_reg = Signal(10)
disp = Signal()
priorities = Signal(max=self.nfifos)
idling = Signal()
# startup sequence
self.fsm.act("WAIT_TX_ENABLE",
If(self.tx_enable.storage,
NextValue(self.tx_idle.word_idx, 0),
NextValue(tx_wordcount, 0),
NextValue(tx_bitcount, 0),
NextState("LOAD_CHAR")
)
)
self.fsm.act("LOAD_CHAR",
NextValue(idling, 1),
NextValue(self.tx_idle.source_ack, 1),
NextValue(tx_reg, self.tx_idle.source_data),
NextValue(disp, self.tx_idle.disp_out),
NextState("START_TX")
)
self.fsm.act("START_TX",
tx_en.eq(1),
If((~self.tx_enable.storage) & (tx_wordcount == 3),
NextState("WAIT_TX_ENABLE")
)
)
self.sync.cxp_upconn += [
self.tx_fifos.disp_in.eq(disp),
self.tx_idle.disp_in.eq(disp),
If(tx_en,
o.eq(tx_reg[0]),
tx_reg.eq(Cat(tx_reg[1:], 0)),
tx_bitcount.eq(tx_bitcount + 1),
# char boundary
If(tx_bitcount == 9,
tx_bitcount.eq(0),
If((~self.tx_fifos.pe.n) & (self.tx_fifos.pe.o == 0),
# trigger packets are inserted at char boundary and don't contribute to word count
tx_reg.eq(self.tx_fifos.source_data[0]),
self.tx_fifos.source_ack[0].eq(1),
disp.eq(self.tx_fifos.disp_out[0]),
).Else(
# word boundary
If(tx_wordcount == 3,
tx_wordcount.eq(0),
If(~self.tx_fifos.pe.n,
# priority lv 1 & 2 packets are inserted at word boundary
idling.eq(0),
priorities.eq(self.tx_fifos.pe.o),
self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]),
).Else(
idling.eq(1),
self.tx_idle.source_ack.eq(1),
tx_reg.eq(self.tx_idle.source_data),
disp.eq(self.tx_idle.disp_out),
)
).Else(
tx_wordcount.eq(tx_wordcount + 1),
If(~idling,
self.tx_fifos.source_ack[priorities].eq(1),
tx_reg.eq(self.tx_fifos.source_data[priorities]),
disp.eq(self.tx_fifos.disp_out[priorities]),
).Else(
self.tx_idle.source_ack.eq(1),
tx_reg.eq(self.tx_idle.source_data),
disp.eq(self.tx_idle.disp_out),
)
),
)
)
).Else(
o.eq(0)
)
]
# DEBUG: remove pads
self.encoded_data = CSRStatus(10)
self.sync.cxp_upconn +=[
If(tx_bitcount == 0,
self.encoded_data.status.eq(tx_reg),
)
]
ninth_bit = Signal()
word_bound = Signal()
p0 = Signal()
p3 = Signal()
self.comb += [
ninth_bit.eq(tx_bitcount == 9),
word_bound.eq(tx_wordcount == 3),
p0.eq(self.tx_idle.word_idx == 0),
p3.eq(self.tx_idle.word_idx == 3),
]
self.specials += [
# # debug sma
# Instance("OBUF", i_I=o, o_O=pads.p_tx),
# Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx),
# # pmod 0-7 pin
# Instance("OBUF", i_I=o, o_O=pmod[0]),
# Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
# Instance("OBUF", i_I=~self.tx_fifos.pe.n, o_O=pmod[2]),
# Instance("OBUF", i_I=ninth_bit, o_O=pmod[3]),
# Instance("OBUF", i_I=word_bound, o_O=pmod[4]),
# Instance("OBUF", i_I=idling, o_O=pmod[5]),
# # Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[6]),
# # Instance("OBUF", i_I=self.tx_fifos.source_ack[2], o_O=pmod[6]),
# # Instance("OBUF", i_I=self.tx_fifos.source_ack[1], o_O=pmod[7]),
# Instance("OBUF", i_I=p0, o_O=pmod[6]),
# Instance("OBUF", i_I=p3, o_O=pmod[7]),
]
self.symbol0 = CSR(9)
self.symbol1 = CSR(9)
self.symbol2 = CSR(9)
self.sync += [
self.tx_fifos.sink_stb[0].eq(self.symbol0.re),
self.tx_fifos.sink_data[0].eq(self.symbol0.r),
self.tx_fifos.sink_stb[1].eq(self.symbol1.re),
self.tx_fifos.sink_data[1].eq(self.symbol1.r),
self.tx_fifos.sink_stb[2].eq(self.symbol2.re),
self.tx_fifos.sink_data[2].eq(self.symbol2.r),
]
class TxFIFOs(Module):
def __init__(self, nfifos, fifo_depth):
self.disp_in = Signal()
self.disp_out = Array(Signal() for _ in range(nfifos))
self.sink_stb = Signal(nfifos)
self.sink_ack = Signal(nfifos)
self.sink_data = [Signal(9) for _ in range(nfifos)]
self.source_ack = Array(Signal() for _ in range(nfifos))
self.source_data = Array(Signal(10) for _ in range(nfifos))
# # #
source_stb = Signal(nfifos)
for i in range(nfifos):
cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
setattr(self.submodules, "tx_fifo" + str(i), fifo)
setattr(self.submodules, "tx_encoder" + str(i), encoder)
self.sync += [
fifo.sink.stb.eq(self.sink_stb[i]),
self.sink_ack[i].eq(fifo.sink.ack),
fifo.sink.data.eq(self.sink_data[i]),
]
self.sync.cxp_upconn += [
encoder.d.eq(fifo.source.data[:8]),
encoder.k.eq(fifo.source.data[8]),
encoder.disp_in.eq(self.disp_in),
self.disp_out[i].eq(encoder.disp_out),
source_stb[i].eq(fifo.source.stb),
fifo.source.ack.eq(self.source_ack[i]),
self.source_data[i].eq(encoder.output),
# reset ack after asserted
If(self.source_ack[i], self.source_ack[i].eq(0)),
]
# FIFOs transmission priority
self.submodules.pe = PriorityEncoder(nfifos)
self.comb += self.pe.i.eq(source_stb)
class TxIdle(Module):
def __init__(self):
self.disp_in = Signal()
self.disp_out = Signal()
self.word_idx = Signal(max=4)
self.source_ack = Signal()
self.source_data = Signal(10)
# # #
# CXP 2.1 section 9.2.5
IDLE_CHARS = Array([
#[char, k]
[0b10111100, 1], #K28.5
[0b00111100, 1], #K28.1
[0b00111100, 1], #K28.1
[0b10111100, 0], #D28.5
])
encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
self.submodules += encoder
self.sync.cxp_upconn += [
encoder.d.eq(IDLE_CHARS[self.word_idx][0]),
encoder.k.eq(IDLE_CHARS[self.word_idx][1]),
encoder.disp_in.eq(self.disp_in),
self.disp_out.eq(encoder.disp_out),
self.source_data.eq(encoder.output),
If(self.source_ack,
# reset after asserted
self.source_ack.eq(0),
If(self.word_idx != 3,
self.word_idx.eq(self.word_idx + 1),
).Else(
self.word_idx.eq(0),
)
),
]

View File

@ -0,0 +1,610 @@
use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
use libboard_zynq::{println, timer::GlobalTimer};
use log::info;
// use log::info;
use crate::pl::csr;
pub struct CXP_DownConn_Settings {
pub rxdiv: u8,
pub qpll_fbdiv: u8,
}
#[derive(Clone, Copy, Debug)]
#[allow(non_camel_case_types)]
pub enum CXP_SPEED {
CXP_1,
CXP_2,
CXP_3,
CXP_5,
CXP_6,
CXP_10,
CXP_12,
}
fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
unsafe {
// send K28_5 for CDR to align
const K28_5: u8 = 0xBC;
const K28_1: u8 = 0x3C;
const D21_5: u8 = 21 | 5 << 5;
// NOTE: testing with IDLE word + manual comma alignment
// 62.5MHz OK
// 125MHz OK
// 156.25MHz
// 250MHz OK
// 312.5MHz
// 500MHz ?? havn't change CDR config yet
const LEN: usize = 4;
const DATA: [[u8; LEN]; 2] = [
// [K28_5, K28_1, K28_5, K28_1],
// [1, 1, 1, 1],
[K28_5, K28_1, K28_1, D21_5],
[1, 1, 1, 0],
];
csr::cxp::downconn_data_0_write(DATA[0][0]);
csr::cxp::downconn_data_1_write(DATA[0][1]);
csr::cxp::downconn_data_2_write(DATA[0][2]);
csr::cxp::downconn_data_3_write(DATA[0][3]);
csr::cxp::downconn_control_bit_0_write(DATA[1][0]);
csr::cxp::downconn_control_bit_1_write(DATA[1][1]);
csr::cxp::downconn_control_bit_2_write(DATA[1][2]);
csr::cxp::downconn_control_bit_3_write(DATA[1][3]);
info!("waiting for tx&rx setup...");
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",
csr::cxp::downconn_txinit_phaligndone_read(),
csr::cxp::downconn_rxinit_phaligndone_read(),
);
// enable txdata tranmission thought MGTXTXP, required by PMA loopback
csr::cxp::downconn_txenable_write(1);
info!("waiting for rx to align...");
// timer.delay_us(50_000);
// while csr::cxp::downconn_rx_ready_read() != 1 {}
// info!("rx ready!");
// println!("0xA8 = {:#06x}", read(0x62));
// write(0x62, 0x001A);
// println!("0xA8 = {:#06x}", read(0x62));
// for _ in 0..20 {
loop {
// NOTE: raw data
let data0 = csr::cxp::downconn_rxdata_0_read();
let data1 = csr::cxp::downconn_rxdata_1_read();
// let rxready = csr::cxp::downconn_rx_ready_read();
// timer.delay_us(100);
// if data0 == 0b0101111100 || data0 == 0b1010000011 {
// println!(
// "data[0] = {:#012b} comma = {} | rx ready = {}",
// data0,
// data0 == 0b0101111100 || data0 == 0b1010000011,
// rxready,
// );
// timer.delay_us(1_000_000);
// } else if data0 == 0b1001111100 || data0 == 0b0110000011 {
// println!(
// "data[0] = {:#012b} K28.1 | rx ready = {}",
// data0,
// rxready,
// );
// timer.delay_us(1_000_000);
// } else {
// println!(
// "data[0] = {:#012b} | rx ready = {}",
// data0,
// rxready,
// );
// timer.delay_us(1_000_000);
// }
println!("0b{:010b}{:010b}", data0, data1);
timer.delay_us(1_000_000);
// NOTE:decode data
// let data0_decoded = csr::cxp::downconn_decoded_data_0_read();
// let data0_k = csr::cxp::downconn_decoded_k_0_read();
// let data1_decoded = csr::cxp::downconn_decoded_data_1_read();
// let data1_k = csr::cxp::downconn_decoded_k_1_read();
// println!(
// "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
// data0_decoded,
// data0_k,
// data1_decoded,
// data1_k,
// );
// timer.delay_us(1_000_000);
}
}
}
pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) {
unsafe {
info!("turning on pmc loopback mode...");
csr::cxp::downconn_loopback_mode_write(0b010); // Near-End PMA Loopback
// QPLL setup
csr::cxp::downconn_qpll_reset_write(1);
info!("waiting for QPLL/CPLL to lock...");
while csr::cxp::downconn_qpll_locked_read() != 1 {}
info!("QPLL locked");
// tx/rx setup
csr::cxp::downconn_tx_start_init_write(1);
csr::cxp::downconn_rx_start_init_write(1);
info!("waiting for tx & rx setup...");
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",
csr::cxp::downconn_txinit_phaligndone_read(),
csr::cxp::downconn_rxinit_phaligndone_read(),
);
println!("==============================================================================");
}
CXP_GTX::change_linerate(timer, speed);
loopback_testing(timer, 0x00, 0);
}
pub mod CXP_GTX {
use super::*;
struct RX_CDR_CFG {
pub cfg_reg0: u16, //0x0A8
pub cfg_reg1: u16, //0x0A9
pub cfg_reg2: u16, //0x0AA
pub cfg_reg3: u16, //0x0AB
pub cfg_reg4: u16, //0x0AC
}
pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
info!("Changing datarate to {:?}", speed);
// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
let settings = txusrclk::get_txusrclk_config(speed);
txusrclk::setup(timer, settings);
change_qpll_settings(speed);
change_cdr_cfg(speed);
unsafe {
csr::cxp::downconn_qpll_reset_write(1);
info!("waiting for QPLL/CPLL to lock...");
while csr::cxp::downconn_qpll_locked_read() != 1 {}
info!("QPLL locked");
}
unsafe {
csr::cxp::downconn_tx_restart_write(1);
csr::cxp::downconn_rx_restart_write(1);
}
}
fn change_qpll_settings(speed: CXP_SPEED) {
match speed {
CXP_SPEED::CXP_12 => {
panic!("CXP 12.5Gbps is not supported on zc706");
}
_ => {}
}
// this switches between High and Low band VCO
// NOT needed if VCO can do 12.5GHz
let qpll_cfg_reg0 = match speed {
// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0181,
CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x01C1,
};
// Change QPLL_REFCLK_DIV
let qpll_div_reg0 = match speed {
// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x8068,
CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0068,
};
// Change QPLL_FBDIV
let qpll_div_reg1 = match speed {
CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120,
CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,
};
println!("0x32 = {:#018b}", qpll_read(0x32));
qpll_write(0x32, qpll_cfg_reg0);
println!("0x32 = {:#018b}", qpll_read(0x32));
println!("0x33 = {:#018b}", qpll_read(0x33));
qpll_write(0x33, qpll_div_reg0);
println!("0x33 = {:#018b}", qpll_read(0x33));
println!("0x36 = {:#018b}", qpll_read(0x36));
qpll_write(0x36, qpll_div_reg1);
println!("0x36 = {:#018b}", qpll_read(0x36));
let divider = match speed {
// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
CXP_SPEED::CXP_1 => 0b100, // Divided by 8
CXP_SPEED::CXP_2 => 0b011, // Divided by 4
CXP_SPEED::CXP_5 | CXP_SPEED::CXP_3 => 0b010, // Divided by 2
CXP_SPEED::CXP_10 | CXP_SPEED::CXP_6 => 0b001, // Divided by 1
CXP_SPEED::CXP_12 => 0b000,
// NOTE: for ZC706 QPLL VCO that go up to 12.5GHz
// CXP_SPEED::CXP_1 => 0b100, // Divided by 8
// CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0b011, // Divided by 4
// CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0b010, // Divided by 2
// CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0b001, // Divided by 1
};
unsafe {
csr::cxp::downconn_rx_div_write(divider);
csr::cxp::downconn_tx_div_write(divider);
}
}
fn change_cdr_cfg(speed: CXP_SPEED) {
// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
let cdr_cfg = match speed {
// Divided by 8
CXP_SPEED::CXP_1 => {
RX_CDR_CFG {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1008, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
cfg_reg3: 0x0000, //0x0AB
cfg_reg4: 0x0003, //0x0AC
}
}
// Divided by 4
CXP_SPEED::CXP_2 => {
RX_CDR_CFG {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1010, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
cfg_reg3: 0x0000, //0x0AB
cfg_reg4: 0x0003, //0x0AC
}
}
// Divided by 2
CXP_SPEED::CXP_3 | CXP_SPEED::CXP_5 => {
RX_CDR_CFG {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1020, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
cfg_reg3: 0x0000, //0x0AB
cfg_reg4: 0x0003, //0x0AC
}
}
// Divided by 1
CXP_SPEED::CXP_6 => {
RX_CDR_CFG {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1040, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
cfg_reg3: 0x0000, //0x0AB
cfg_reg4: 0x0003, //0x0AC
}
}
// Divided by 1
CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
RX_CDR_CFG {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1040, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
cfg_reg3: 0x0000, //0x0AB
cfg_reg4: 0x000B, //0x0AC
}
}
};
gtx_write(0x0A8, cdr_cfg.cfg_reg0);
gtx_write(0x0A9, cdr_cfg.cfg_reg1);
gtx_write(0x0AA, cdr_cfg.cfg_reg2);
gtx_write(0x0AB, cdr_cfg.cfg_reg3);
gtx_write(0x0AC, cdr_cfg.cfg_reg4);
}
fn gtx_read(address: u16) -> u16 {
// DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
unsafe {
csr::cxp::downconn_gtx_daddr_write(address);
csr::cxp::downconn_gtx_dread_write(1);
while (csr::cxp::downconn_gtx_dready_read() != 1) {}
csr::cxp::downconn_gtx_dout_read()
}
}
fn gtx_write(address: u16, value: u16) {
// DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
unsafe {
csr::cxp::downconn_gtx_daddr_write(address);
csr::cxp::downconn_gtx_din_write(value);
csr::cxp::downconn_gtx_din_stb_write(1);
while (csr::cxp::downconn_gtx_dready_read() != 1) {}
}
}
fn qpll_read(address: u8) -> u16 {
unsafe {
csr::cxp::downconn_qpll_daddr_write(address);
csr::cxp::downconn_qpll_dread_write(1);
while (csr::cxp::downconn_qpll_dready_read() != 1) {}
csr::cxp::downconn_qpll_dout_read()
}
}
fn qpll_write(address: u8, value: u16) {
unsafe {
csr::cxp::downconn_qpll_daddr_write(address);
csr::cxp::downconn_qpll_din_write(value);
csr::cxp::downconn_qpll_din_stb_write(1);
while (csr::cxp::downconn_qpll_dready_read() != 1) {}
}
}
}
pub mod txusrclk {
use super::*;
pub struct PLLSetting {
pub clkout0_reg1: u16, //0x08
pub clkout0_reg2: u16, //0x09
pub clkfbout_reg1: u16, //0x14
pub clkfbout_reg2: u16, //0x15
pub div_reg: u16, //0x16
pub lock_reg1: u16, //0x18
pub lock_reg2: u16, //0x19
pub lock_reg3: u16, //0x1A
pub power_reg: u16, //0x28
pub filt_reg1: u16, //0x4E
pub filt_reg2: u16, //0x4F
}
fn one_clock_cycle() {
unsafe {
csr::cxp::downconn_pll_dclk_write(1);
csr::cxp::downconn_pll_dclk_write(0);
}
}
fn set_addr(address: u8) {
unsafe {
csr::cxp::downconn_pll_daddr_write(address);
}
}
fn set_data(value: u16) {
unsafe {
csr::cxp::downconn_pll_din_write(value);
}
}
fn set_enable(en: bool) {
unsafe {
let val = if en { 1 } else { 0 };
csr::cxp::downconn_pll_den_write(val);
}
}
fn set_write_enable(en: bool) {
unsafe {
let val = if en { 1 } else { 0 };
csr::cxp::downconn_pll_dwen_write(val);
}
}
fn get_data() -> u16 {
unsafe { csr::cxp::downconn_pll_dout_read() }
}
fn drp_ready() -> bool {
unsafe { csr::cxp::downconn_pll_dready_read() == 1 }
}
#[allow(dead_code)]
fn read(address: u8) -> u16 {
set_addr(address);
set_enable(true);
// Set DADDR on the mmcm and assert DEN for one clock cycle
one_clock_cycle();
set_enable(false);
while !drp_ready() {
// keep the clock signal until data is ready
one_clock_cycle();
}
get_data()
}
fn write(address: u8, value: u16) {
set_addr(address);
set_data(value);
set_write_enable(true);
set_enable(true);
// Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
one_clock_cycle();
set_write_enable(false);
set_enable(false);
while !drp_ready() {
// keep the clock signal until write is finished
one_clock_cycle();
}
}
fn reset(rst: bool) {
unsafe {
let val = if rst { 1 } else { 0 };
csr::cxp::downconn_txpll_reset_write(val)
}
}
pub fn setup(timer: &mut GlobalTimer, settings: PLLSetting) {
if false {
info!("0x08 = {:#06x}", read(0x08));
info!("0x09 = {:#06x}", read(0x09));
info!("0x14 = {:#06x}", read(0x14));
info!("0x15 = {:#06x}", read(0x15));
info!("0x16 = {:#06x}", read(0x16));
info!("0x18 = {:#06x}", read(0x18));
info!("0x19 = {:#06x}", read(0x19));
info!("0x1A = {:#06x}", read(0x1A));
info!("0x28 = {:#06x}", read(0x28));
info!("0x4E = {:#06x}", read(0x4E));
info!("0x4F = {:#06x}", read(0x4F));
} else {
// Based on "DRP State Machine" from XAPP888
// hold reset HIGH during pll config
reset(true);
write(0x08, settings.clkout0_reg1);
write(0x09, settings.clkout0_reg2);
write(0x14, settings.clkfbout_reg1);
write(0x15, settings.clkfbout_reg2);
write(0x16, settings.div_reg);
write(0x18, settings.lock_reg1);
write(0x19, settings.lock_reg2);
write(0x1A, settings.lock_reg3);
write(0x28, settings.power_reg);
write(0x4E, settings.filt_reg1);
write(0x4F, settings.filt_reg2);
reset(false);
// wait for the pll to lock
timer.delay_us(100);
let locked = unsafe { csr::cxp::downconn_txpll_locked_read() == 1 };
info!("txusrclk locked = {}", locked);
}
}
pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
match speed {
CXP_SPEED::CXP_1 => {
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 32
// TXUSRCLK=62.5MHz
PLLSetting {
clkout0_reg1: 0x1410, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1104, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x5801, //0x19
lock_reg3: 0xdbe9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9808, //0x4E
filt_reg2: 0x9100, //0x4F
}
}
CXP_SPEED::CXP_2 => {
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
// TXUSRCLK=62.5MHz
PLLSetting {
clkout0_reg1: 0x1208, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1104, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x5801, //0x19
lock_reg3: 0xdbe9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9808, //0x4E
filt_reg2: 0x9100, //0x4F
}
}
CXP_SPEED::CXP_3 => {
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
// TXUSRCLK=78.125MHz
PLLSetting {
clkout0_reg1: 0x1208, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1145, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x7001, //0x19
lock_reg3: 0xf3e9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9908, //0x4E
filt_reg2: 0x1900, //0x4F
}
}
CXP_SPEED::CXP_5 => {
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
// TXUSRCLK=125MHz
PLLSetting {
clkout0_reg1: 0x1104, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1104, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x5801, //0x19
lock_reg3: 0xdbe9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9808, //0x4E
filt_reg2: 0x9100, //0x4F
}
}
CXP_SPEED::CXP_6 => {
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
// TXUSRCLK=156.25MHz
PLLSetting {
clkout0_reg1: 0x1104, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1145, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x7001, //0x19
lock_reg3: 0xf3e9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9908, //0x4E
filt_reg2: 0x1900, //0x4F
}
}
CXP_SPEED::CXP_10 => {
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
// TXUSRCLK=250MHz
PLLSetting {
clkout0_reg1: 0x1082, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1104, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x5801, //0x19
lock_reg3: 0xdbe9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9808, //0x4E
filt_reg2: 0x9100, //0x4F
}
}
CXP_SPEED::CXP_12 => {
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
// TXUSRCLK=312.5MHz
PLLSetting {
clkout0_reg1: 0x1082, //0x08
clkout0_reg2: 0x0000, //0x09
clkfbout_reg1: 0x1145, //0x14
clkfbout_reg2: 0x0000, //0x15
div_reg: 0x1041, //0x16
lock_reg1: 0x03e8, //0x18
lock_reg2: 0x7001, //0x19
lock_reg3: 0xf3e9, //0x1A
power_reg: 0x0000, //0x28
filt_reg1: 0x9908, //0x4E
filt_reg2: 0x1900, //0x4F
}
}
}
}
}

View File

@ -0,0 +1,88 @@
use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
use libboard_zynq::{println, timer::GlobalTimer};
use crate::pl::csr;
pub fn crc_test() {
let arr = [
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, // CXP CRC-32
0x56, 0x86, 0x5D, 0x6f,
];
let mut crc: u32; // seed = 0xFFFFFFFF
unsafe {
csr::cxp::crc_en_write(1);
for a in arr.iter() {
csr::cxp::crc_data_write(*a);
crc = csr::cxp::crc_value_read();
println!("input = {:#04x}", *a);
println!("CRC NOT(val.reverse) = {:#010x}", !crc.reverse_bits());
// since the input bit are reversed when entering the crc engine, the output char need to be reversed to cancel out on the receiver side
println!("CRC CXP = {:#010x}", crc);
}
}
}
pub fn tx_test(timer: &mut GlobalTimer) {
// the 8bit shift is k symbol
// const K28_1: u16 = 0x3C | (1 << 8);
// const K28_5: u16 = 0xBC | (1 << 8);
const D31_1: u16 = 0x3F;
const D01_1: u16 = 0x21;
const LEN: usize = 100;
let mut arr: [u16; LEN] = [0; LEN];
unsafe {
csr::cxp::upconn_clk_reset_write(1);
// csr::cxp::upconn_bitrate2x_enable_write(1);
csr::cxp::upconn_clk_reset_write(0);
loop {
// TODO: verify the char & word boundary thingy
for _ in 0..8 {
csr::cxp::upconn_symbol1_write(D01_1);
}
for _ in 0..4 {
csr::cxp::upconn_symbol2_write(D31_1);
}
timer.delay_us(1);
csr::cxp::upconn_tx_enable_write(1);
for i in 0..LEN {
arr[i] = get_encoded();
}
for i in 0..LEN {
match arr[i] {
0b1010111001 | 0b0101001001 => {
println!("encoded = {:#012b} D31.1", arr[i])
}
0b0111011001 | 0b1000101001 => {
println!("encoded = {:#012b} D01.1", arr[i])
}
0b0011111010 | 0b1100000101 => {
println!("encoded = {:#012b} K28.5 start idling....", arr[i])
}
0b0011111001 | 0b1100000110 => {
println!("encoded = {:#012b} K28.1 idling...", arr[i])
}
0b0011101010 => {
println!("encoded = {:#012b} D28.5 END idle", arr[i])
}
_ => {
println!("encoded = {:#012b}", arr[i])
}
}
}
println!("-------------------------------------");
csr::cxp::upconn_tx_enable_write(0);
timer.delay_us(2_000_000);
}
}
fn get_encoded() -> u16 {
unsafe { csr::cxp::upconn_encoded_data_read().reverse_bits() >> 6 }
}
}

View File

@ -42,6 +42,11 @@ pub mod si5324;
pub mod si549; pub mod si549;
use core::{cmp, str}; use core::{cmp, str};
#[cfg(has_cxp)]
pub mod cxp_downconn;
#[cfg(has_cxp)]
pub mod cxp_upconn;
pub fn identifier_read(buf: &mut [u8]) -> &str { pub fn identifier_read(buf: &mut [u8]) -> &str {
unsafe { unsafe {
pl::csr::identifier::address_write(0); pl::csr::identifier::address_write(0);