forked from M-Labs/artiq-zynq
cxp downconn: use auto aligner
cxp downconn: fix autoaligner checking
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0e69c5d5ba
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1f8ef6bf96
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@ -8,8 +8,8 @@ from misoc.interconnect.csr import *
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from operator import add
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from functools import reduce
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from operator import add
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class CXP_DownConn(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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@ -101,13 +101,12 @@ class CXP_DownConn(Module, AutoCSR):
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=gtx.clk_aligner.rxslide, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.clk_aligner.rxinit_done, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.clk_aligner.restart, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_aligned, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.clk_aligner.ready, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_det_reset, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=gtx.clk_aligner.comma_det.detected, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=gtx.comma_det.aligner_en_rxclk, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.comma_det.rxinit_done, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.comma_det.comma_aligned, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.comma_det.ready, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=gtx.comma_det.valid_data, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[7]),
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]
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@ -260,157 +259,106 @@ class QPLL(Module):
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)
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]
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# detect if the comma is located at data[0:10]
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class Comma_Detector(Module):
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def __init__(self, comma, width):
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self.reset = Signal()
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self.data = Signal(width)
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self.detected = Signal()
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self.bitshift = Signal(max=width)
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self.comma_aligned = Signal()
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# # #
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last_data = Signal(10)
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data = Signal(width+10)
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comma_n = ~comma & 0b1111111111
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self.sync += [
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last_data.eq(self.data[:10]),
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data.eq(Cat(self.data, last_data)),
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If(self.reset,
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self.bitshift.eq(0),
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self.detected.eq(0),
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),
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If(self.reset,
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self.comma_aligned.eq(0)
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).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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self.comma_aligned.eq(1)
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),
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]
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for n in range(width):
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self.sync += \
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If((data[n:n+10] == comma) | (data[n:n+10] == comma_n),
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self.bitshift.eq(width-n),
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self.detected.eq(1),
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)
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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# 50000 62.5MHz locks | 125MHz takes a lot time to locks | 250MHz many commas
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# 30000 62.5MHz & 125MHz locks | 250MHz more commas but not lock
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# 30000 62.5MHz & 125MHz locks | 250MHz nothing to see
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# 27000 62.5MHz & 125MHz locks | 250MHz nothing to see
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# 25000 62.5MHz takes long time to lock | 125MHz no lock | 250MHz locks
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# 24700 62.5MHz lock | 125MHz sometimes locks | 250MHz locks
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# 20000 250MHz nothing to see
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# 10000 62.5MHz & 125MHz nothing to see | 250MHz many commas not much can survive the second check
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class Manual_Aligner(Module):
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def __init__(self, comma, check_period=24_700, width=20):
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self.rxslide = Signal()
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class Comma_Detector(Module):
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def __init__(self, comma, check_period=50_000, width=20):
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self.data = Signal(width)
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self.rxinit_done = Signal()
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self.aligner_en_rxclk = Signal()
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self.ready = Signal()
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self.restart = Signal()
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# # #
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timerout_period = 5_000_000
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timerout = Signal(reset=timerout_period-1, max=timerout_period)
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ready_rxclk = Signal()
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self.specials += MultiReg(ready_rxclk, self.ready)
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self.ready.attr.add("no_retiming")
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restart_sys = Signal()
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restart_rxclk = Signal()
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self.specials += MultiReg(restart_rxclk, restart_sys)
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restart_sys.attr.add("no_retiming")
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# NOTE: be careful of all the timeout values!!! It should be much larger than the longest fsm
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# TODO: fix comma fall too fast for 500MHz (10Gpbs) -> need to change CDR_CFG via DRP
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# Restart rx periodically since rx need to be restart when connecting RXN/RXP
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self.sync += [
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self.restart.eq(0),
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If(restart_sys,
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timerout.eq(timerout.reset),
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self.restart.eq(1),
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).Elif(~self.ready,
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If((timerout == 0),
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timerout.eq(timerout.reset),
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self.restart.eq(1),
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).Else(
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timerout.eq(timerout - 1),
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)
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)
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]
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self.comma_det_reset = Signal()
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self.comma_aligned = Signal()
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self.valid_data = Signal()
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self.submodules.recheck_ps = recheck_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
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aligned = Signal()
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self.specials += MultiReg(self.comma_aligned, aligned)
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valid_data = Signal()
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self.specials += MultiReg(self.valid_data, valid_data)
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comma_n = ~comma & 0b1111111111
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rx1cnt = Signal(max=11)
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self.sync.cxp_gtx_rx += [
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If(self.comma_det_reset,
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rx1cnt.eq(reduce(add, [self.data[i] for i in range(10)])),
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If(recheck_ps.o,
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self.comma_aligned.eq(0)
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).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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self.comma_aligned.eq(1)
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),
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If(recheck_ps.o,
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self.valid_data.eq(0)
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).Elif((rx1cnt == 4) | (rx1cnt == 5) | (rx1cnt == 6),
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self.valid_data.eq(1)
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),
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]
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self.submodules.fsm = fsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="IDLE"))
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check_counter = Signal(reset=check_period-1, max=check_period)
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check = Signal()
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aligner_en_sys = Signal()
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self.specials += MultiReg(aligner_en_sys, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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self.sync += [
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check.eq(0),
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If(check_counter == 0,
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check_counter.eq(check_counter.reset),
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check.eq(1),
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).Else(
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check_counter.eq(check_counter - 1),
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)
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]
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rxinit_done_rxclk = Signal()
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self.specials += MultiReg(self.rxinit_done, rxinit_done_rxclk, odomain="cxp_gtx_rx")
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check_timer = Signal(reset=check_period-1,max=check_period)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.comma_det_reset.eq(1),
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If(rxinit_done_rxclk,
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NextValue(check_timer, check_timer.reset),
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NextState("WAIT_COMMA_DET"),
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),
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aligner_en_sys.eq(1),
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If(check,
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recheck_ps.i.eq(1),
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If(aligned,
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NextState("WAIT_NO_ERROR"),
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).Else(
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self.restart.eq(1),
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)
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)
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)
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fsm.act("WAIT_COMMA_DET",
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NextValue(check_timer, check_timer - 1),
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If(check_timer == 0,
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restart_rxclk.eq(1),
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NextState("RESET"),
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# restart_ps.i.eq(1),
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# NextState("IDLE"),
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).Elif(self.comma_aligned,
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NextValue(check_timer, check_timer.reset),
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self.comma_det_reset.eq(1),
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NextState("READY")
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fsm.act("WAIT_NO_ERROR",
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aligner_en_sys.eq(1),
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If(check,
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recheck_ps.i.eq(1),
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If(aligned & valid_data,
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NextState("READY"),
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).Else(
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self.restart.eq(1),
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NextState("IDLE"),
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)
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)
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)
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fsm.act("READY",
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ready_rxclk.eq(1),
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If(check_timer == 0,
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NextValue(check_timer, check_timer.reset),
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self.comma_det_reset.eq(1),
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If(~self.comma_aligned,
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restart_rxclk.eq(1),
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NextState("RESET"),
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# restart_ps.i.eq(1),
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# NextState("IDLE"),
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self.ready.eq(1),
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If(check,
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recheck_ps.i.eq(1),
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If(~(aligned & valid_data),
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self.restart.eq(1),
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NextState("IDLE"),
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)
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).Else(
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NextValue(check_timer, check_timer - 1),
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)
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)
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fsm.act("RESET",
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restart_rxclk.eq(1),
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)
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class GTX(Module):
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@ -466,7 +414,7 @@ class GTX(Module):
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txdata = Signal(20)
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rxdata = Signal(20)
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rxslide = Signal()
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comma_align_en = Signal()
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# Note: the following parameters were set after consulting AR45360
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self.specials += \
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Instance("GTXE2_CHANNEL",
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@ -558,7 +506,7 @@ class GTX(Module):
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i_RXDFEXYDEN=1,
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i_RXDFEXYDHOLD=0,
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i_RXDFEXYDOVRDEN=0,
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i_RXLPMEN=1, # RXLPMEN = 1: LPM mode is enabled for non scramble data
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i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled for non scramble data
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p_RX_DFE_GAIN_CFG=0x0207EA,
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p_RX_DFE_VP_CFG=0b00011111100000011,
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p_RX_DFE_UT_CFG=0b10001000000000000,
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@ -597,18 +545,17 @@ class GTX(Module):
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_ENABLE=0b1111111111,
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p_ALIGN_COMMA_WORD=2, # allow rxslide to shift 20 times
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p_ALIGN_MCOMMA_DET="FALSE",
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_VALUE=0b1010000011,
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p_ALIGN_PCOMMA_DET="FALSE",
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p_ALIGN_PCOMMA_DET="TRUE",
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p_ALIGN_PCOMMA_VALUE=0b0101111100,
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p_SHOW_REALIGN_COMMA="FALSE",
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p_RXSLIDE_AUTO_WAIT=7,
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p_RXSLIDE_MODE="PCS",
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p_RXSLIDE_MODE="OFF",
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p_RX_SIG_VALID_DLY=10,
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i_RXPCOMMAALIGNEN=0,
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i_RXMCOMMAALIGNEN=0,
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i_RXCOMMADETEN=0, # enable manual word alignment
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i_RXSLIDE=rxslide,
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i_RXPCOMMAALIGNEN=comma_align_en,
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i_RXMCOMMAALIGNEN=comma_align_en,
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i_RXCOMMADETEN=1, # enable auto word alignment
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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@ -735,13 +682,13 @@ class GTX(Module):
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]
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self.submodules.clk_aligner = clk_aligner = Manual_Aligner(0b0101111100)
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self.submodules.comma_det = comma_det = Comma_Detector(0b0101111100)
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self.comb += [
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clk_aligner.data.eq(rxdata),
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clk_aligner.rxinit_done.eq(rx_init.done),
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rxslide.eq(clk_aligner.rxslide),
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self.rx_ready.eq(clk_aligner.ready),
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comma_det.data.eq(rxdata),
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comma_det.rxinit_done.eq(rx_init.done),
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comma_align_en.eq(comma_det.aligner_en_rxclk),
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self.rx_ready.eq(comma_det.ready),
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rx_init.restart.eq(self.rx_restart | clk_aligner.restart),
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rx_init.restart.eq(self.rx_restart | comma_det.restart),
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tx_init.restart.eq(self.tx_restart),
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]
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