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cxp downconn fw: add idle data

This commit is contained in:
morgan 2024-07-26 15:24:35 +08:00
parent faef1d2dff
commit 4ba1c5ef2e
1 changed files with 49 additions and 9 deletions
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58
src/libboard_artiq/src/cxp_downconn.rs
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@ -17,9 +17,6 @@ pub fn main(timer: &mut GlobalTimer) {
timer.delay_us(50_000);
info!("tx_phaligndone = {} ", csr::cxp::txinit_phaligndone_read(),);
// enable txdata tranmission thought MGTXTXP, required by PMA loopback
csr::cxp::txenable_write(1);
loopback_testing(timer, 0x00, 0);
}
@ -27,17 +24,54 @@ pub fn main(timer: &mut GlobalTimer) {
unsafe {
// send K28_5 for CDR to align
const K28_5: u8 = 0xBC;
csr::cxp::data_0_write(K28_5);
csr::cxp::control_bit_0_write(1);
csr::cxp::data_1_write(K28_5);
csr::cxp::control_bit_1_write(1);
const K28_1: u8 = 0x3C;
const D21_5: u8 = 21 << 5 | 5;
// brute force aligner only align K28_5 on rxdata[:10]
// don't send too much K28_5 in case phase is locked on the wrong stuff
// seems like I need at least 2 K28_5 to work
// NOTE: testing with IDLE word + buildin comma alignment
// 62.5MHz OK
// 125MHz OK
// 156.25MHz OK
// 250MHz
// 312.5MHz
const LEN: usize = 8;
const DATA: [[u8; LEN]; 2] = [
// [K28_5, K28_5, K28_5, K28_1, K28_5, K28_5, K28_5, K28_5],
// [1, 1, 1, 1, 1, 1, 1, 1],
[K28_5, K28_1, K28_1, D21_5, K28_5, K28_1, K28_1, D21_5],
[1, 1, 1, 0, 1, 1, 1, 0],
];
csr::cxp::data_0_write(DATA[0][0]);
csr::cxp::data_1_write(DATA[0][1]);
csr::cxp::data_2_write(DATA[0][2]);
csr::cxp::data_3_write(DATA[0][3]);
csr::cxp::data_4_write(DATA[0][4]);
csr::cxp::data_5_write(DATA[0][5]);
csr::cxp::data_6_write(DATA[0][6]);
csr::cxp::data_7_write(DATA[0][7]);
csr::cxp::control_bit_0_write(DATA[1][0]);
csr::cxp::control_bit_1_write(DATA[1][1]);
csr::cxp::control_bit_2_write(DATA[1][2]);
csr::cxp::control_bit_3_write(DATA[1][3]);
csr::cxp::control_bit_4_write(DATA[1][4]);
csr::cxp::control_bit_5_write(DATA[1][5]);
csr::cxp::control_bit_6_write(DATA[1][6]);
csr::cxp::control_bit_7_write(DATA[1][7]);
// enable txdata tranmission thought MGTXTXP, required by PMA loopback
csr::cxp::txenable_write(1);
info!("waiting for rx to align...");
while csr::cxp::rx_ready_read() != 1 {}
timer.delay_us(50_000);
info!("rx ready!");
csr::cxp::data_1_write(data);
csr::cxp::control_bit_1_write(control_bit);
// csr::cxp::data_3_write(data);
// csr::cxp::control_bit_3_write(control_bit);
println!(
"data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
csr::cxp::data_0_read(),
@ -69,3 +103,9 @@ pub fn main(timer: &mut GlobalTimer) {
}
}
}
pub fn change_linerate() {
// TODO: switch CPLL/QPLL divider for RXUSRCLK
// TODO: switch pll for TXUSRCLK = freq(linerate)/20
// TODO: reset tx&rx for phase alignment
}