forked from M-Labs/artiq-zynq
cxp downconn: fix aligner not work @ 5 & 6.25Gbps
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aa128e1467
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a6b1701de3
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@ -160,7 +160,7 @@ class CXP_DownConn(Module, AutoCSR):
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=gtx.comma_det.rxinit_done, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.comma_det.word_aligned, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.comma_det.aligner_en_rxclk, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.comma_det.check_reset, o_O=pmod_pads[3]),
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@ -331,7 +331,7 @@ class QPLL(Module):
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class Comma_Detector(Module):
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def __init__(self, comma, check_period=1_000_000):
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self.data = Signal(20)
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self.rxinit_done = Signal()
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self.word_aligned = Signal()
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self.aligner_en_rxclk = Signal()
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self.ready = Signal()
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@ -345,39 +345,6 @@ class Comma_Detector(Module):
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# - UG476 (v1.12.1) p.228
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# The validity of data & comma are checked externally
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# aligned = Signal()
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# valid_data = Signal()
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# aligned_rxclk = Signal()
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# valid_data_rxclk = Signal()
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# rx1cnt = Signal(max=11)
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# self.specials += [
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# MultiReg(aligned_rxclk, aligned),
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# MultiReg(valid_data_rxclk, valid_data),
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# ]
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# self.submodules.check_reset = check_reset = PulseSynchronizer("sys", "cxp_gtx_rx")
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# comma_n = ~comma & 0b1111111111
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# self.sync.cxp_gtx_rx += [
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# If(check_reset.o,
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# aligned_rxclk.eq(0),
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# ).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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# aligned_rxclk.eq(1),
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# ),
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# rx1cnt.eq(reduce(add, [self.data[i] for i in range(10)])),
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# If(check_reset.o,
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# valid_data_rxclk.eq(0),
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# ).Elif((rx1cnt == 4) | (rx1cnt == 5) | (rx1cnt == 6),
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# valid_data_rxclk.eq(1),
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# ),
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# ]
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# self.aligned = Signal()
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# self.valid_data = Signal()
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# self.comb +=[
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# self.aligned.eq(aligned),
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# self.valid_data.eq(valid_data)
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# ]
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check_counter = Signal(reset=check_period-1, max=check_period)
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@ -465,18 +432,31 @@ class Comma_Detector(Module):
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self.submodules.rxfsm = rxfsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="ALIGNING"))
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# the data from gtxe2 is delayed and checking at the output may not reflect the alignment inside the aligner
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# thus, failing to alignment on high linerate >5Gbps is common due to the aligner_en being asserted longer than necessary and lead to a lose of lock
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# a timer is used to wait till the "aligned" data to arrive and do a system check like the datasheet suggested
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self.submodules.timer = timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(5000))
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rxfsm.act("ALIGNING",
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self.aligner_en_rxclk.eq(1),
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If(comma_aligned & (~has_error),
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If(self.word_aligned,
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check_reset.eq(1),
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NextState("DOUBLE_CHECK"),
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NextState("WAIT_ALIGNED_DATA"),
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)
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)
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rxfsm.act("DOUBLE_CHECK",
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rxfsm.act("WAIT_ALIGNED_DATA",
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timer.wait.eq(1),
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If(timer.done,
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check_reset.eq(1),
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NextState("CHECKING"),
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)
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)
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rxfsm.act("CHECKING",
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If(check,
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check_reset.eq(1),
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If(~error_seen,
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If(comma_seen & (~error_seen),
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NextState("READY"),
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).Else(
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NextState("ALIGNING")
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@ -490,62 +470,12 @@ class Comma_Detector(Module):
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ready.eq(1),
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If(check,
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check_reset.eq(1),
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If(~comma_seen,
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If(~(comma_seen & (~error_seen)),
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NextState("ALIGNING"),
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)
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)
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)
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# self.submodules.fsm = fsm = FSM(reset_state="WAIT_RXINIT")
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# aligner_en = Signal()
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# self.specials += MultiReg(aligner_en, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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# fsm.act("WAIT_RXINIT",
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# If(self.rxinit_done,
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# NextState("WAIT_COMMA_ALIGN"),
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# )
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# )
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# fsm.act("WAIT_COMMA_ALIGN",
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# aligner_en.eq(1),
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# If(check,
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# check_reset.i.eq(1),
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# If(aligned,
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# NextState("WAIT_VALID_DATA"),
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# ).Else(
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# self.restart.eq(1),
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# NextState("WAIT_RXINIT")
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# )
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# )
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# )
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# fsm.act("WAIT_VALID_DATA",
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# aligner_en.eq(1),
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# If(check,
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# check_reset.i.eq(1),
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# If(aligned & valid_data,
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# NextState("READY"),
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# ).Else(
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# self.restart.eq(1),
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# NextState("WAIT_RXINIT"),
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# )
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# )
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# )
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# fsm.act("READY",
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# self.ready.eq(1),
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# If(check,
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# check_reset.i.eq(1),
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# If(~(aligned & valid_data),
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# self.restart.eq(1),
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# NextState("WAIT_RXINIT"),
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# )
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# )
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# )
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class GTX(Module):
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# Settings:
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@ -609,6 +539,7 @@ class GTX(Module):
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txdata = Signal(40)
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rxdata = Signal(40)
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word_aligned = Signal()
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comma_aligner_en = Signal()
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# Note: the following parameters were set after consulting AR45360
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self.specials += \
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@ -752,6 +683,7 @@ class GTX(Module):
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i_RXMCOMMAALIGNEN=comma_aligner_en,
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i_RXCOMMADETEN=1,
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i_RXSLIDE=0,
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o_RXBYTEISALIGNED=word_aligned,
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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@ -893,7 +825,7 @@ class GTX(Module):
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self.submodules.comma_det = comma_det = Comma_Detector(0b0101111100)
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self.comb += [
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comma_det.data.eq(rxdata),
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comma_det.rxinit_done.eq(rx_init.done),
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comma_det.word_aligned.eq(word_aligned),
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comma_aligner_en.eq(comma_det.aligner_en_rxclk),
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self.rx_ready.eq(comma_det.ready),
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