morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp downconn fw: add qpll linerate change

This commit is contained in:
morgan 2024-08-01 12:33:22 +08:00
parent 5a40422f1d
commit 4436dc930e
1 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/libboard_artiq/src/cxp_downconn.rs
View File

@ -131,13 +131,14 @@ pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) {
csr::cxp::downconn_tx_start_init_write(1);
csr::cxp::downconn_rx_start_init_write(1);
info!("waiting for tx setup...");
info!("waiting for tx & rx setup...");
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",
csr::cxp::downconn_txinit_phaligndone_read(),
csr::cxp::downconn_rxinit_phaligndone_read(),
);
println!("==============================================================================");
}
change_linerate(timer, speed);
@ -146,9 +147,11 @@ pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) {
}
pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
// TODO: switch QPLL divider for RXUSRCLK
// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
let settings = txusrclk::get_txusrclk_config(speed);
txusrclk::setup(timer, settings);
// TODO: set TX/RXDIV via TX/RXRATE
// TODO: set TX/RX DIVIDER via TX/RXRATE
change_qpll_settings(speed);
unsafe {
@ -158,13 +161,9 @@ pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
info!("QPLL locked");
}
// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
let settings = txusrclk::get_txusrclk_config(speed);
txusrclk::setup(timer, settings);
// reset tx&rx for phase alignment
unsafe {
// csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset
csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset
csr::cxp::downconn_rx_restart_write(1); // <--- NOTE: this doesn't do anything atm
}
}