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artiq-zynq
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775 Commits 16 Branches 0 Tags 4.2 MiB
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519 Commits

Author SHA1 Message Date
morgan cb1ec7f62a CXP upconn: remove unused code 2024-06-17 14:46:49 +08:00
morgan 48d3a9cd4a CXP up connection gw: init 2024-06-17 13:19:37 +08:00
morgan 96a052513d zc706: use new CXP file name 2024-06-14 17:18:26 +08:00
morgan b2c6c20426 cxp: refactor to its separte module 2024-06-14 17:17:56 +08:00
morgan 5fcf5cb70f cxp gtx: rename to cxp_downconn 2024-06-14 17:17:16 +08:00
morgan 47e1a83519 cxp fmc: rename file 2024-06-14 17:16:51 +08:00
morgan d592825284 CXP gtx: rename to CXP DownConn 2024-06-14 17:07:58 +08:00
morgan b52589bd5f CXP CLK alignment: clock domain naming refactor 2024-06-13 16:56:36 +08:00
morgan 9c69167f7f CXP gtx: Clock domain naming refactor and remove cxp_gtx 2024-06-13 16:56:16 +08:00
morgan 8ac71b37a9 CXP GTX: init 2024-06-12 14:50:38 +08:00
morgan ce0e14879c Gateware: ZC706 CXP GTX setup 2024-06-05 13:02:52 +08:00
morgan df7feb3b17 Gateware: CXP_GTX init 2024-06-05 13:02:52 +08:00
morgan f5c604bbb5 zc706: add USER LED to allow compilation 2024-06-05 13:02:29 +08:00
morgan d61d7a5a95 zc706: add CXP FMC variant 2024-06-05 13:02:29 +08:00
morgan 681d7400c7 FMCIO: add cxp_4r adepter io 2024-06-05 13:02:29 +08:00
morgan 586fd2f17e Gateware: remove redundant si549.py & wrpll.py 2024-05-30 15:27:16 +08:00
morgan 377f8779a0 kasli soc: refactor to use wrpll from artiq 2024-05-30 15:25:33 +08:00
mwojcik 2b2ebb5354 aux: increase max payload size 2024-05-20 15:20:06 +08:00
morgan 35ea0ed2ca WRPLL: add filter for DRTIO 100MHz 2024-05-08 18:50:55 +08:00
morgan cdf4ff24c0 WRPLL: replace PI controller with new filter 2024-05-08 18:50:55 +08:00
morgan 285b02c4b1 WRPLL: remove anti-windup 2024-05-08 18:50:55 +08:00
morgan 53cb592d19 kasli soc: add rtio_frequency cfg for runtime 2024-05-08 16:14:56 +08:00
morgan 1d603c73b7 DDMTD: replace 1st edge to median edge deglitcher 2024-04-29 13:05:02 +08:00
morgan 61315c29b9 Si549: recalibrate TAG_OFFSET for ISERDESE2 2024-04-29 13:03:30 +08:00
morgan 3f57de6ec7 DDMTD: replace FD with ISERDESE2 2024-04-29 13:03:30 +08:00
morgan cca23aa2a5 wrpll runtime: reduce mmcm output jitter 
rtio_clocking: update mmcm setting to use HIGH bandwidth
 2024-04-29 11:20:50 +08:00
morgan 2bbaea3ad5 SMAFreqMulti: set mmcm bw to HIGH for lower jitter 2024-04-29 11:20:50 +08:00
mwojcik 0a19f8fb89 satman: revert async flag changes 2024-04-26 11:37:14 +08:00
mwojcik a30c7d1f3a runtime: drtio aux refactoring, revert async flag 2024-04-26 11:37:14 +08:00
mwojcik 2d10503c20 libboard_artiq: support multiple aux rx buffers 2024-04-24 17:12:57 +08:00
mwojcik 92a29051f7 drtio_aux_controller: support aux_buffer_count 2024-04-24 17:12:39 +08:00
morgan 14fa038118 Firmware: Runtime WRPLL 
runtime: drive CLK_SEL to true when si549 is used
runtime & libboard_artiq: allow standalone to use io_expander
si549: add bit bang mmcm dynamic configuration
si549: add frequency counter for refclk
rtio_clocking & si549: add 125Mhz wrpll refclk setup
 2024-04-12 16:38:46 +08:00
morgan b81323af30 Firmware: Satman skew calibration & tester 
cargo template: add calibrate_wrpll_skew feature
tag collector: add TAG_OFFSET for Satman WRPLL
tag collector: add TAG_OFFSET getter & setter for calibration
wrpll: add skew tester and calibration
wrpll: gate calibration behind calibrate_wrpll_skew feature
 2024-04-12 16:38:46 +08:00
morgan 291777f764 Firmware: Satman WRPLL 
satman: drive CLK_SEL to true when si549 is used
satman : add main & helper si549 setup
satman : add WRPLL select_recovered_clock
si549: add tag collector to process gtx & main tags
si549: add frequency counter to set BASE_ADPLL
si549: add set_adpll for main & helper PLL
si549: add main & helper PLL
FIQ & si549: replace dummy with a custom handler for gtx & main tags ISR
 2024-04-12 16:38:39 +08:00
morgan a1d80fb93b Firmware: Si549 and io_expander 
io_expander: set CLK_SEL pin to output when si549 is used
io_expander: gate virtual leds for standalone
si549: add bit bang i2c
si549: add si549 programming
si549: add main & helper setup
 2024-04-11 15:18:10 +08:00
morgan 7827c7b803 Gateware: kasli_soc WRPLL setup 
kasli_soc: use enable_wrpll from json to switch from si5324 to si549
kasli_soc: add wrpll for all variants
kasli_soc: add gtx & main tag nFIQ for all variants
kasli_soc: add clk_synth_se for master & satellite
kasli_soc: add wrpll_refclk for runtime
kasli_soc: add skewtester for satman
kasli_soc: add WRPLL_REF_CLK config for firmware
 2024-04-11 15:18:10 +08:00
morgan e4d8d44c7c Gateware: WRPLL 
ddmtd: add DDMTD and deglitcher
wrpll: add helper clockdomain
wrpll: add frequency counter
wrpll: add skewtester
wrpll: add gtx & main tag collection
wrpll: add gtx & main tag eventmanager for shared peripheral interrupt
wrpll: add SMA frequency multiplier to generate 125Mhz refclk
si549: add i2c and adpll programmer
 2024-04-11 15:18:04 +08:00
morgan 4455f740d2 main: set exception vector table addr 
linker: add exceptions start & end symbol
 2024-03-07 15:37:42 +08:00
morgan 63bf1c81d4 fiq: use dummy handler to fix compilation error 2024-03-07 13:26:52 +08:00
mwojcik bfb582f99b cargo fmt 2024-02-01 14:43:41 +08:00
mwojcik 52e64fb2f9 subkernel: use negative ID for argument passing 2024-02-01 14:43:41 +08:00
mwojcik facc98058c subkernel: fix DMA return control to wrong master 2024-02-01 14:43:41 +08:00
mwojcik f0f81dbf8a subkernel: support no-timeout, message passing 2024-02-01 14:43:41 +08:00
mwojcik 30e6bf4a3a subkernel: add support for (d)dma 2024-01-11 12:33:02 +08:00
mwojcik 8f4e30dd9c satman: support sub-subkernels, routing 2024-01-11 12:33:02 +08:00
mwojcik e31a31c4ff master: drtioaux: 
- support async flag
- source in packets
- rerouting packets
 2024-01-11 12:33:02 +08:00
mwojcik 6ca1719033 comms: fix compilation on standalone 2023-11-14 14:08:31 +08:00
mwojcik aebc739c1e add support for tar flashable (sub)kernels 2023-11-13 11:24:23 +08:00
linuswck e1b2c45813 kasli_soc & zc706: Fix GTX Clock Path during INIT 2023-11-07 18:55:08 +08:00
linuswck e6372b9766 zynq_clocking: Allow ext signal to set cur_clk csr 
- for example, current_clock csr can be connected to tx_init.done
 2023-11-07 18:55:08 +08:00