57852cb3a1
zc706: add CXP_DEMO variant
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zc706: add fmc pads
zc706: add constraint to fix comma alignment & setup/hold time issue
zc706: add csr & mem group for cxp
zc706: add CXP to rtio_channel
zc706: add frame buffer pipeline
2025-01-09 15:56:10 +08:00
0054075089
cxp: add PHY and pipeline
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testing: add loopback tx for rx testing
testing: add trigger, trigger ack for testing
cxp: add upconn & downconn phy
cxp: add upconn & downconn pipeline
cxp: add rtlink
cxp: add test packet & error counter CSR
cxp: fix ch1 rx mem cannot be read
cxp: add frame buffer to use KiB instead of KB
2025-01-09 15:56:10 +08:00
9aefdc569d
cxp frame pipeline: frame handling pipeline
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pipeline: add eop marker, cxp_crc32 checker
frame: add stream crossbar, double buffer, parser
frame: add metadata parser, frame extractor
frame: add stream arbiter, crc checker & broadcaster
frame: add custom pixel gearbox 32:8*4
2025-01-09 15:56:10 +08:00
4cd10ef7be
cxp pipeline: packet handling pipeline
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tx pipeline: add CRC32 inserter
tx pipeline: add start & end of packet code inserter
tx pipeline: add packet wrapper for start & stop packet indication
tx pipeline: add code source for trigger & trigger ack packet
tx pipeline: add packet for trigger & trigger ack
tx pipeline: add test packet generator
tx pipeline: add tx_command_packet for firmware
tx command packet: add dma to store control packet
rx pipeline: add reciever path
rx pipeline: add duplicate char decoder
rx pipeline: add trig ack checker
rx pipeline: add packet decoder
decoder: add test packet checher
decoder: add packet DMA
2025-01-09 15:56:10 +08:00
90864a12b7
cxp upconn gw: add low speed serial PHY
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testing: add debug fifo output b4 encoder
cxp upconn: add low speed serial
cxp upconn: add reset, tx_busy, tx_enable
cxp upconn: add clockgen module for 20.83Mbps & 41.66Mbps using counters
cxp upconn: add oserdes using CEInserter
cxp upconn gw: remove unused debug pad
2024-12-12 11:49:54 +08:00
2ea2b5e922
cxp downconn gw: add gtx up to 12.5Gbps
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testing: add txusrclk mmcm & loopback mode
testing: add debug output
testing: send comma in the middle of long packet to maintain lock
downconn: don't put IDLE into fifo
downconn: add GTX and QPLL support
downconn: add DRP for GTX and QPLL to support all CXP linerates
GTX: add gtx with mmcm for TXUSRCLK freq requirement
GTX: add loopback mode parameter for testing
GTX: add gtx with 40bits internal width
GTX: use built-in comma aligner
GTX: add comma checker to ensure comma is aligner on highest linerate
GTX: set QPLL as CLK source for GTX
GTX: add multilane rx support with the same rx reseter
2024-12-12 11:49:54 +08:00
70e994ce3b
fmc: add cxp_4r_fmc adepter io
2024-12-04 16:08:47 +08:00
c9d7d47c91
temp diagrams & unused sim
2024-12-04 16:08:47 +08:00
d79bf8d54a
gateware: Add default TTLs to EBAZ4205 ( #335 )
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Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>
2024-11-16 10:40:45 +08:00
a410c40b50
ADD SPI to EBAZ4205 for AD9834 ( #331 )
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Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>
2024-10-17 15:06:11 +08:00
61df939c87
ebaz4205: add variant and hydra job
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Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>
2024-10-08 11:35:31 +08:00
81790257a5
Add ebaz4205 support ( #327 )
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Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>
2024-10-05 15:05:49 +08:00
23857eef63
allow toggling SED spread with flash config key
2024-07-09 18:11:20 +08:00
586fd2f17e
Gateware: remove redundant si549.py & wrpll.py
2024-05-30 15:27:16 +08:00
377f8779a0
kasli soc: refactor to use wrpll from artiq
2024-05-30 15:25:33 +08:00
53cb592d19
kasli soc: add rtio_frequency cfg for runtime
2024-05-08 16:14:56 +08:00
1d603c73b7
DDMTD: replace 1st edge to median edge deglitcher
2024-04-29 13:05:02 +08:00
3f57de6ec7
DDMTD: replace FD with ISERDESE2
2024-04-29 13:03:30 +08:00
2bbaea3ad5
SMAFreqMulti: set mmcm bw to HIGH for lower jitter
2024-04-29 11:20:50 +08:00
92a29051f7
drtio_aux_controller: support aux_buffer_count
2024-04-24 17:12:39 +08:00
7827c7b803
Gateware: kasli_soc WRPLL setup
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kasli_soc: use enable_wrpll from json to switch from si5324 to si549
kasli_soc: add wrpll for all variants
kasli_soc: add gtx & main tag nFIQ for all variants
kasli_soc: add clk_synth_se for master & satellite
kasli_soc: add wrpll_refclk for runtime
kasli_soc: add skewtester for satman
kasli_soc: add WRPLL_REF_CLK config for firmware
2024-04-11 15:18:10 +08:00
e4d8d44c7c
Gateware: WRPLL
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ddmtd: add DDMTD and deglitcher
wrpll: add helper clockdomain
wrpll: add frequency counter
wrpll: add skewtester
wrpll: add gtx & main tag collection
wrpll: add gtx & main tag eventmanager for shared peripheral interrupt
wrpll: add SMA frequency multiplier to generate 125Mhz refclk
si549: add i2c and adpll programmer
2024-04-11 15:18:04 +08:00
e1b2c45813
kasli_soc & zc706: Fix GTX Clock Path during INIT
2023-11-07 18:55:08 +08:00
e6372b9766
zynq_clocking: Allow ext signal to set cur_clk csr
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- for example, current_clock csr can be connected to tx_init.done
2023-11-07 18:55:08 +08:00
07044752b6
zynq_clocking: add ext_async_rst to AsyncRstSYNCR
2023-11-07 18:55:08 +08:00
79fc5a7789
zynq_clocking: expose mmcm_locked for SYSCRG
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- mmcm_locked -> self.mmcm_locked
2023-11-07 18:55:08 +08:00
b768d5648c
Add grabber module
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-10-16 14:35:20 +08:00
136e24f597
kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1
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- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
2023-10-11 16:45:26 +08:00
b15322b6ba
kasli_soc: Add support for shuttler on gateware
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- Port from artiq repo
- Add EEM_DRTIO gateware
2023-10-10 11:22:05 +08:00
8fd1306145
zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
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- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
2023-10-10 11:21:34 +08:00
49205eea17
satellite gateware: add kernel rtio to cri
2023-10-09 11:36:23 +08:00
656cbf4546
kasli_soc: use sed_lanes value from HW description
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https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
2023-10-06 15:37:56 +01:00
ae3099dd8e
kasli_soc: support 100MHz clock
2023-10-06 16:27:25 +08:00
b3856e879b
refactor write_rustc_cfg_file()
2023-09-11 11:48:19 +08:00
1ccae0d442
consolidate all write..file() into config.py
2023-09-11 11:48:19 +08:00
2c19f4ac31
replace rustc_cfg[ ] & change write_rustc_cfg_file
2023-09-11 11:48:19 +08:00
MorganTL
0e6309b95e
change write_rustc_cfg_file to follow artiq repo
2023-08-30 14:56:12 +08:00
622d267d55
add virtual LEDs, improve IO expander setup, drive TX_DISABLE
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-08-28 16:08:10 +08:00
4ae8557018
drtio: remame drtio_transceiver to gt_drtio
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Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
2023-08-28 13:05:40 +08:00
ca17cd419e
Revert "kasli_soc: add SFP0..3 LED indication"
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This reverts commit 5111778363
2023-08-03 10:42:09 +08:00
5111778363
kasli_soc: add SFP0..3 LED indication
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-07-24 16:30:14 +08:00
ee438105b2
json: base -> drtio_role
2023-06-16 17:03:25 +08:00
63594d7e3d
update configuration of IBUFDS_GTE2
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Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 12:08:41 +08:00
ad076dd4e9
zc706: fix satellite analyzer target
2023-05-24 09:52:16 +08:00
c536a70890
satellite gateware: add rtio analyzer
2023-05-22 15:23:24 +08:00
b747abe83c
qc2: add 4 edge counters to the end of rtio
2023-04-03 12:25:07 +08:00
4b1ce1a6ff
satellites: add rtio_dma, connect as cri master
2023-03-21 15:54:58 +08:00
dce37a52aa
KasliSoC satellite: fix serdes timing
2023-02-20 13:07:42 +08:00
46b2687d70
RTIO/SYS Clock merge
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Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2023-02-17 15:52:43 +08:00
19e60073de
kasli_soc: ident = variant name
2022-10-21 11:55:24 +08:00
