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bors[bot] aab69aa37f
Merge #128 #129 
128: build(deps): bump cortex-m from 0.6.2 to 0.6.3 r=jordens a=dependabot[bot]

Bumps [cortex-m](https://github.com/rust-embedded/cortex-m) from 0.6.2 to 0.6.3.
<details>
<summary>Release notes</summary>
<p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m/releases">cortex-m's releases</a>.</em></p>
<blockquote>
<h2>v0.6.3</h2>
<h3>Added</h3>
<ul>
<li>Initial Cortex-M Security Extension support for armv8m</li>
<li><code>UDF</code> intrinsic</li>
<li>Methods to enable/disable exceptions in SCB</li>
</ul>
<h3>Fixed</h3>
<ul>
<li>Fix bug in <code>asm::delay</code> not updating status clobber flags</li>
<li>Swapped to <code>llvm_asm!</code> to support inline assembly on new nightlies</li>
<li>Our precompiled assembly routines have additional debug information</li>
<li>ITM <code>is_fifo_ready</code> improved to support armv8</li>
<li>Cache enabling moved to pre-built assembly routines to prevent possible
undefined behaviour</li>
</ul>
</blockquote>
</details>
<details>
<summary>Changelog</summary>
<p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m/blob/v0.6.3/CHANGELOG.md">cortex-m's changelog</a>.</em></p>
<blockquote>
<h2>[v0.6.3] - 2020-07-20</h2>
<h3>Added</h3>
<ul>
<li>Initial Cortex-M Security Extension support for armv8m</li>
<li><code>UDF</code> intrinsic</li>
<li>Methods to enable/disable exceptions in SCB</li>
</ul>
<h3>Fixed</h3>
<ul>
<li>Fix bug in <code>asm::delay</code> not updating status clobber flags</li>
<li>Swapped to <code>llvm_asm!</code> to support inline assembly on new nightlies</li>
<li>Our precompiled assembly routines have additional debug information</li>
<li>ITM <code>is_fifo_ready</code> improved to support armv8</li>
<li>Cache enabling moved to pre-built assembly routines to prevent possible
undefined behaviour</li>
</ul>
</blockquote>
</details>
<details>
<summary>Commits</summary>
<ul>
<li><a href="39ee96635c"><code>39ee966</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/250">#250</a></li>
<li><a href="2e44cd8071"><code>2e44cd8</code></a> Bump version to 0.6.3</li>
<li><a href="358be5df90"><code>358be5d</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/249">#249</a></li>
<li><a href="6717d4bc77"><code>6717d4b</code></a> Update CHANGELOG with 0.6.3 backports</li>
<li><a href="202cb2d885"><code>202cb2d</code></a> Always link pre-built asm, required for new cache management functions</li>
<li><a href="b7ff5f7fe4"><code>b7ff5f7</code></a> Allow the taken flag to be optimized out</li>
<li><a href="cb6a61adf3"><code>cb6a61a</code></a> Add a function to get SHCSR enable bit positions</li>
<li><a href="b607b35faf"><code>b607b35</code></a> Use assembly sequences to enable caches.</li>
<li><a href="33f031868d"><code>33f0318</code></a> Correct the documentation for the <code>SCB::set_pendst</code> function</li>
<li><a href="f58e5e1374"><code>f58e5e1</code></a> ITM: don't test reserved bits in is_fifo_ready</li>
<li>Additional commits viewable in <a href="https://github.com/rust-embedded/cortex-m/compare/v0.6.2...v0.6.3">compare view</a></li>
</ul>
</details>
<br />


[![Dependabot compatibility score](https://dependabot-badges.githubapp.com/badges/compatibility_score?dependency-name=cortex-m&package-manager=cargo&previous-version=0.6.2&new-version=0.6.3)](https://help.github.com/articles/configuring-automated-security-fixes)

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</details>

129: build(deps): bump cortex-m-log from 0.6.1 to 0.6.2 r=jordens a=dependabot[bot]

Bumps [cortex-m-log](https://github.com/DoumanAsh/cortex-m-log) from 0.6.1 to 0.6.2.
<details>
<summary>Commits</summary>
<ul>
<li>See full diff in <a href="https://github.com/DoumanAsh/cortex-m-log/commits">compare view</a></li>
</ul>
</details>
<br />


[![Dependabot compatibility score](https://dependabot-badges.githubapp.com/badges/compatibility_score?dependency-name=cortex-m-log&package-manager=cargo&previous-version=0.6.1&new-version=0.6.2)](https://help.github.com/articles/configuring-automated-security-fixes)

Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting `@dependabot rebase`.

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You can trigger Dependabot actions by commenting on this PR:
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</details>

Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
 		2020-08-11 12:59:24 +00:00
.cargo Fixing changes 2020-04-22 15:59:08 +02:00
.github dependabot: update 2020-06-22 15:07:57 +02:00
ad9959 style: implement a couple clippy suggestions [nfc] 2020-06-17 14:57:09 +02:00
doc cargo: tweak 2019-03-29 19:34:31 +01:00
src fmt 2020-06-23 14:55:59 +02:00
.gitignore start 2019-03-18 12:56:26 +01:00
.rustfmt.toml travis: clippy and rustfmt 2019-11-24 15:10:01 +01:00
CHANGELOG.md add changelog 2019-05-28 13:23:31 +02:00
Cargo.lock Merge #128 #129 2020-08-11 12:59:24 +00:00
Cargo.toml Merge #119 2020-08-08 09:32:40 +00:00
LICENSE readme, license 2019-03-20 18:33:35 +00:00
README.md gha, readme: partially revert 0fdfb45 2020-06-16 17:32:28 +02:00
cargosha256.nix update cargosha256 2020-05-26 17:01:09 +08:00
memory.x ethernet: tweak 2019-04-28 14:06:56 +00:00
openocd.gdb Updating structure, adding DMA triggered transfers 2020-06-08 18:11:14 +02:00
pounder_test.py Renaming pounder test script 2020-06-11 19:10:02 +02:00
stabilizer.cfg Fixing changes 2020-04-22 15:59:08 +02:00
stabilizer.py cleanup, robustify 2019-05-28 10:15:20 +00:00
stabilizer_pid.png png 2019-05-09 16:40:35 +02:00
stabilizer_pid.svg README: diagram and photo 2019-05-09 16:05:36 +02:00

README.md

Continuous Integration

Stabilizer Firmware

Flow diagram

Hardware

Features

  • dual channel
  • SPI ADC
  • SPI DAC
  • 500 kHz rate, timed sampling
  • 2 µs latency, unmatched between channels
  • f32 IIR math
  • generic biquad (second order) IIR filter
  • anti-windup
  • derivative kick avoidance

Limitations/TODOs

  • Fixed AFE gains
  • The IP and MAC address are hardcoded
  • Expose configurable limits
  • 100Base-T only
  • Digital IO, GPIO header, AFE header, EEM header are not handled

Hardware

See https://github.com/sinara-hw/Stabilizer

Minimal bootstrapping documentation

  • Clone or download this
  • Get rustup
  • Get cargo-binutils
  • rustup target add thumbv7em-none-eabihf
  • cargo build --release
  • Do not try the debug (default) mode. It is guaranteed to panic.

Using GDB/OpenOCD

  • Get a recent openocd, a JTAG adapter ("st-link" or some clone) and everything connected and permissions setup. Most Nucleo boards have a detachable ST-Link v2 and are cheap.1
  • Get a multiarch gdb (or a cross arm gdb and edit .cargo/config accordingly)
  • openocd -f stabilizer.cfg and leave it running
  • cargo run --release

Using USB-DFU

  • Install the DFU USB tool (dfu-util)
  • Connect to the Micro USB connector below the RJ45
  • Short JC2/BOOT
  • cargo objcopy --release --bin stabilizer -- -O binary stabilizer.bin or arm-none-eabi-objcopy -O binary target/thumbv7em-none-eabihf/release/stabilizer stabilizer.bin
  • dfu-util -a 0 -s 0x08000000:leave -D stabilizer.bin

Using ST-Link virtual mass storage

  • cargo objcopy --release --bin stabilizer -- -O binary stabilizer.bin or arm-none-eabi-objcopy -O binary target/thumbv7em-none-eabihf/release/stabilizer stabilizer.bin
  • Connect the ST-Link debugger
  • copy stabilizer.bin to the NODE_H743ZI USB disk

Protocol

Stabilizer can be configured via newline-delimited JSON over TCP. It listens on port 1235. stabilizer.py contains a reference implementation of the protocol.

  1. Build a cable: connect a standard 8 conductor ribbon with the wires numbered 1-8 to the pins on the St-Link v2 single row 2.54mm connector as 647513(82) ((i) marks an unused wire) and to the 1.27mm dual row on Stabilizer as 657483x2x1 (x marks an unused pin, enumeration is standard for dual row, as in the schematic). It's just folding the ribbon between wires 5 and 6. The signals on the ribbon are then NRST,TDI,TDO,TCK,TMS,3V3,GND,GND. ↩︎