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f250e036ca
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rpll: simplify parameters, add one test
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2021-02-04 12:46:33 +01:00 |
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dcc71d5d11
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iir: tweak math a bit
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2021-02-02 15:41:47 +01:00 |
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f02d3cc95b
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dsp: clippy
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2021-02-01 18:46:21 +01:00 |
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2a84e3f299
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dsp: remove unused code, let the compiler decide about inlining
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2021-02-01 18:37:05 +01:00 |
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5d7266abbc
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dsp: clippy
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2021-02-01 18:24:51 +01:00 |
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b6e22b576b
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iir: add const fn new()
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2021-02-01 17:18:10 +01:00 |
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ab7e3d229b
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rpll: clean up asserts
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2021-02-01 16:01:05 +01:00 |
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65a3f839a0
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lockin: remove feed()
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2021-02-01 13:42:38 +01:00 |
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965c6335e1
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dsp: fmt
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2021-02-01 12:40:12 +01:00 |
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7748d8eb54
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dsp: constructor style
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2021-02-01 12:37:44 +01:00 |
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2c60103696
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dsp: accu: add, iir: rename IIRState to Vec5
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2021-02-01 12:23:47 +01:00 |
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0fd4b167b4
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complex/cossin: decouple modules
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2021-02-01 12:07:03 +01:00 |
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2d43b8970b
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lockin: cleanup
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2021-01-31 20:49:14 +01:00 |
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47089c267c
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dsp: align iir and iir_int, add iir micro benches
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2021-01-31 19:12:24 +01:00 |
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43342cef91
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rpll: docs
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2021-01-31 18:21:47 +01:00 |
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d281783f2e
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rpll: reduce code
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2021-01-31 18:10:13 +01:00 |
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82c8fa1a07
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rpll: extend tests
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2021-01-31 17:10:03 +01:00 |
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ab20d67a07
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rpll: remove redundant time tracking
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2021-01-31 13:42:15 +01:00 |
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6b2d8169f0
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rpll: more/cleaner tests
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2021-01-31 13:25:01 +01:00 |
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be7aad1b81
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rpll: add unittest
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2021-01-30 20:49:31 +01:00 |
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0d1b237202
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complex: richer API
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2021-01-30 18:05:54 +01:00 |
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36288225b3
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rpll: extend to above-nyquist frequencies
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2021-01-28 22:21:42 +01:00 |
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1749d48ca3
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Revert "rpll: auto-align counter"
This reverts commit dbacc5293e12f712fef7bd85848e1b0bd8fde823.
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2021-01-27 09:01:07 +01:00 |
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45e7d6de3c
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rpll: auto-align counter
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2021-01-27 09:01:07 +01:00 |
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7c1fa9695a
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iir lowpass: f32 is sufficient
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2021-01-26 19:37:05 +01:00 |
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73c98c947a
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iir_int: remove spurious note
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2021-01-26 19:23:23 +01:00 |
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2b439a0231
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lockin: remove broken tests, to be rewritten
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2021-01-26 19:22:02 +01:00 |
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d1f41b3ad5
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int_iir: use taylor for lowpass
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2021-01-26 19:19:09 +01:00 |
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7b9fc3b2b3
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iir_int: move lowpass coefficient calculation to iirstate
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2021-01-26 18:51:20 +01:00 |
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9b3a47e08b
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rpll: refine, simplify, document and comment
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2021-01-26 18:49:31 +01:00 |
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ea7b08fc64
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rpll: refine
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2021-01-26 14:40:44 +01:00 |
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16009c3b7e
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rpll: update lockin integration test
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2021-01-25 12:00:47 +01:00 |
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9f9744b9e6
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rpll: implement
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2021-01-25 11:45:59 +01:00 |
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df337f85b8
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reciprocal_pll -> rpll
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2021-01-25 09:54:56 +01:00 |
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57a5c4ff9b
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make lockin a unittest, not integration test
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2021-01-22 16:04:02 +01:00 |
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d0d2c6352d
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lockin: refactor to use common lockin processing
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2021-01-22 16:00:05 +01:00 |
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0cd2140668
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rafactor complex, cossin, atan2
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2021-01-21 16:12:59 +01:00 |
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948e58c910
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lockin: refactor Lockin
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2021-01-21 14:57:44 +01:00 |
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20488ea3bc
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lockin: refine
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2021-01-19 11:01:21 +01:00 |
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Matt Huszagh
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9a3c9afa7e
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fix reciprocal_pll divide error when reference frequency is 0
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2021-01-14 14:51:07 -08:00 |
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Matt Huszagh
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9f0b3eb77e
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fix shift_round overflow error
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2021-01-14 14:51:07 -08:00 |
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Matt Huszagh
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9697560404
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reciprocal_pll: remove unneeded type cast
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2021-01-13 09:08:16 -08:00 |
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Matt Huszagh
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76088efda5
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dsp: add reciprocal_pll
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2021-01-13 08:37:33 -08:00 |
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Matt Huszagh
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80ed715f5a
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shift sin/cos before demodulation product to avoid i64
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2021-01-12 16:07:04 -08:00 |
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Matt Huszagh
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41ea2ebed4
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use round up half integer rounding
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2021-01-12 15:59:03 -08:00 |
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Matt Huszagh
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e14aa8b613
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move lock-in code to main.rs
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2021-01-12 10:45:34 -08:00 |
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Matt Huszagh
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891aad3f17
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remove debug_assert in divide_round
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2021-01-12 07:43:28 -08:00 |
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Matt Huszagh
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31d23a3e0c
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lock-in: use same method for batch_index branching in both instances
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2021-01-12 07:36:56 -08:00 |
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Matt Huszagh
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bae295140d
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update lock-in for integer math and PLL
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2021-01-12 07:36:56 -08:00 |
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Matt Huszagh
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13543ce048
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pll update input is named "x" not "input"
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2021-01-04 11:14:27 -08:00 |
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