78: build(deps): bump cortex-m-rt from 0.6.11 to 0.6.12 r=jordens a=dependabot-preview[bot]
Bumps [cortex-m-rt](https://github.com/rust-embedded/cortex-m-rt) from 0.6.11 to 0.6.12.
<details>
<summary>Changelog</summary>
<p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m-rt/blob/v0.6.12/CHANGELOG.md">cortex-m-rt's changelog</a>.</em></p>
<blockquote>
<h2>[v0.6.12] - 2020-01-26</h2>
<h3>Fixed</h3>
<ul>
<li>Fixed lint warnings getting emitted on macro-generated code.</li>
</ul>
</blockquote>
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<li><a href="17ea2ee386"><code>17ea2ee</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m-rt/issues/242">#242</a></li>
<li><a href="00d300b2e9"><code>00d300b</code></a> Update changelog for 0.6.12</li>
<li><a href="24afb1d0ce"><code>24afb1d</code></a> Bump crate versions</li>
<li><a href="f31ec87545"><code>f31ec87</code></a> Update error message to pass compile-fail tests</li>
<li><a href="b25b619abe"><code>b25b619</code></a> Add a test that enables ALL the warnings</li>
<li><a href="0b2704b070"><code>0b2704b</code></a> <code>#[allow(missing_docs)]</code> on <code>#[pre_init]</code> hooks</li>
<li><a href="431f6d85bf"><code>431f6d8</code></a> Added missing hidden doc</li>
<li><a href="4741844640"><code>4741844</code></a> Hide trampolines from docs</li>
<li>See full diff in <a href="https://github.com/rust-embedded/cortex-m-rt/compare/v0.6.11...v0.6.12">compare view</a></li>
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79: build(deps): bump heapless from 0.5.2 to 0.5.3 r=jordens a=dependabot-preview[bot]
Bumps [heapless](https://github.com/japaric/heapless) from 0.5.2 to 0.5.3.
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<p><em>Sourced from <a href="https://github.com/japaric/heapless/blob/master/CHANGELOG.md">heapless's changelog</a>.</em></p>
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<h2>[v0.5.3] - 2020-01-27</h2>
<h3>Added</h3>
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<li><a href="7de6f7907d"><code>7de6f79</code></a> Extend the ARMv7-A <code>Pool</code> support to the bare-metal <code>armv7a-</code> targets.</li>
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74: build(deps): bump serde from 1.0.103 to 1.0.104 r=jordens a=dependabot-preview[bot]
Bumps [serde](https://github.com/serde-rs/serde) from 1.0.103 to 1.0.104.
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> ## v1.0.104
> - Revert stabilization of Serialize/Deserialize impls for `!` to account for [rust-lang/rust#67224](https://github-redirect.dependabot.com/rust-lang/rust/pull/67224)
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- [`234fbfd`](234fbfd7e3) Release 1.0.104
- [`b9909ce`](b9909cef3d) Revert "Remove never_type feature gate"
- [`d540e72`](d540e72fc7) Format with rustfmt 2019-10-07
- [`13d0899`](13d0899776) Add missing import in de_enum expand test
- [`4fefa7a`](4fefa7a01d) Format imports in expandtest inputs
- [`9048660`](90486607a1) Update test suite to nightly-2019-11-26
- [`0b303c7`](0b303c766c) Mark tests ignored on emscripten rather than omitting
- [`c371563`](c371563bfc) Reduce nesting of macrotest test cases
- [`d17d8eb`](d17d8eb3ee) Rely on std::process::Command's path search
- [`bcaebdb`](bcaebdb2b7) Merge pull request [#1662](https://github-redirect.dependabot.com/serde-rs/serde/issues/1662) from eupn/use-macrotest
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72: build(deps): bump cortex-m-rt from 0.6.10 to 0.6.11 r=jordens a=dependabot-preview[bot]
Bumps [cortex-m-rt](https://github.com/rust-embedded/cortex-m-rt) from 0.6.10 to 0.6.11.
<details>
<summary>Changelog</summary>
*Sourced from [cortex-m-rt's changelog](https://github.com/rust-embedded/cortex-m-rt/blob/master/CHANGELOG.md).*
> ## [v0.6.11] - 2019-12-04
>
> ### Changed
>
> - Macros now generate a second trampoline function instead of randomizing the
> function's symbol name. This makes the build deterministic.
> - [breaking-change] `static mut` resources no longer have `'static` lifetime
> except in the `#[entry]` function (this is a soundness fix; see [#212](https://github-redirect.dependabot.com/rust-embedded/cortex-m-rt/issues/212)).
>
> [#212](https://github-redirect.dependabot.com/rust-embedded/cortex-m-rt/issues/212): [rust-embedded/cortex-m-rt#212](https://github-redirect.dependabot.com/rust-embedded/cortex-m-rt/issues/212)
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- [`5b4ece5`](5b4ece5a1a) Merge [#221](https://github-redirect.dependabot.com/rust-embedded/cortex-m-rt/issues/221)
- [`e2f7532`](e2f7532c4a) cortex-m-rt 0.6.11
- [`06969e5`](06969e5ded) cortex-m-rt-macros 0.1.7
- [`54b7888`](54b7888141) Merge [#219](https://github-redirect.dependabot.com/rust-embedded/cortex-m-rt/issues/219)
- [`0c1322d`](0c1322d287) Inline attr. macro docs and fix links
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- [`0ae866a`](0ae866a286) travis: disable cache
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- [`18a14f4`](18a14f490a) CI: Add shebangs and address shellcheck warnings
- [`1efe5ef`](1efe5efcf5) Add changelog entries
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68: build(deps): bump serde from 1.0.102 to 1.0.103 r=jordens a=dependabot-preview[bot]
Bumps [serde](https://github.com/serde-rs/serde) from 1.0.102 to 1.0.103.
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*Sourced from [serde's releases](https://github.com/serde-rs/serde/releases).*
> ## v1.0.103
> - Support deserializing untagged unit variants from formats that treat unit as None ([#1668](https://github-redirect.dependabot.com/serde-rs/serde/issues/1668))
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- [`97a98a7`](97a98a7031) Test only deser for untagged unit visit_none
- [`533fb9c`](533fb9cc44) Remove never_type feature gate
- [`59b99d2`](59b99d2d60) Move test for untagged-variant-from-unit where it belongs
- [`c796dae`](c796daed7c) Fix test for untagged unit variant
- [`6e2c385`](6e2c385fa5) Allow untagged unit variants to deserialize from `Visitor::visit_none()`
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This was triggered by moving log_init and adding i2c_init on top of
the existing ethernet setup/init after the timer setup and enable.
Thanks @cjbe for debugging.
Also move the RCC peripheral enable calls out of i2c and eth setup.
close#55
supersedes #62
49: fix memory safety issue in ethernet interface (closes#33) r=jordens a=cjbe
The CPU is allowed to implement normal memory writes out-of-order. Here
the write to the OWN flag in the DMA descriptor (normal memory) was
placed after the DMA tail pointer advance (in device memory, so not
reorderable). This meant the ethernet DMA engine stalled as it saw
a descriptor it did not own, and only restarted and sent the packet
when the next packet was released.
This fix will work as long as the CPU data cache is disabled. If we
want to enable the cache, the simplest method would be to mark SRAM3
as uncacheable via the MPU.
Co-authored-by: Chris Ballance <chris.ballance@physics.ox.ac.uk>
The CPU is allowed to access normal memory writes out-of-order. Here
the write to the OWN flag in the DMA descriptor (normal memory) was
placed after the DMA tail pointer advance (in device memory, so not
reorderable). This meant the ethernet DMA engine stalled as it saw
a descriptor it did not own, and only restarted and sent the packet
when the next packet was released.
This fix will work as long as the CPU data cache is disabled. If we
want to enable the cache, the simplest method would be to mark SRAM3
as uncacheable via the MPU.
