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bors[bot] 8045c19f53
Merge #49 
49: fix memory safety issue in ethernet interface (closes #33) r=jordens a=cjbe

The CPU is allowed to implement normal memory writes out-of-order. Here
the write to the OWN flag in the DMA descriptor (normal memory) was
placed after the DMA tail pointer advance (in device memory, so not
reorderable). This meant the ethernet DMA engine stalled as it saw
a descriptor it did not own, and only restarted and sent the packet
when the next packet was released.

This fix will work as long as the CPU data cache is disabled. If we
want to enable the cache, the simplest method would be to mark SRAM3
as uncacheable via the MPU.

Co-authored-by: Chris Ballance <chris.ballance@physics.ox.ac.uk>
 		2019-11-16 07:26:22 +00:00
.cargo cargo: gdb-multicarch 2019-03-20 09:48:44 +00:00
.github try github actions 2019-09-11 17:28:53 +02:00
doc cargo: tweak 2019-03-29 19:34:31 +01:00
src fix memory safety issue in ethernet interface (closes #33) 2019-11-16 03:25:42 +00:00
.gitignore start 2019-03-18 12:56:26 +01:00
.travis.yml travis: try nightly as well 2019-11-11 11:31:39 +01:00
CHANGELOG.md add changelog 2019-05-28 13:23:31 +02:00
Cargo.lock build(deps): bump cortex-m-rtfm from v0.5.0-beta.1 to v0.5.0 2019-11-15 04:38:21 +00:00
Cargo.toml build(deps): bump cortex-m-rtfm from v0.5.0-beta.1 to v0.5.0 2019-11-15 04:38:21 +00:00
LICENSE readme, license 2019-03-20 18:33:35 +00:00
README.md use stable rust (1.38.0) 2019-10-22 13:43:49 +00:00
cargosha256.nix update cargosha256 2019-11-15 11:23:21 +08:00
memory.x ethernet: tweak 2019-04-28 14:06:56 +00:00
openocd.gdb openocd.gdb: modern gdb is stricter 2019-10-22 13:44:04 +00:00
stabilizer.cfg working 2019-03-18 13:10:00 +00:00
stabilizer.py cleanup, robustify 2019-05-28 10:15:20 +00:00
stabilizer_pid.png png 2019-05-09 16:40:35 +02:00
stabilizer_pid.svg README: diagram and photo 2019-05-09 16:05:36 +02:00

README.md

Stabilizer Firmware

Flow diagram

Hardware

Features

  • dual channel
  • SPI ADC
  • SPI DAC
  • 500 kHz rate, timed sampling
  • 2 µs latency, unmatched between channels
  • f32 IIR math
  • generic biquad (second order) IIR filter
  • anti-windup
  • derivative kick avoidance

Limitations/TODOs

  • Fixed AFE gains
  • The IP and MAC address are hardcoded
  • Expose configurable limits
  • 100Base-T only
  • Digital IO, GPIO header, AFE header, EEM header are not handled

Hardware

See https://github.com/sinara-hw/Stabilizer

Minimal bootstrapping documentation

  • Clone or download this
  • Get rustup
  • rustup target add thumbv7em-none-eabihf
  • cargo build --release
  • Do not try the debug (default) mode. It is guaranteed to panic.

Using GDB/OpenOCD

  • Get a recent openocd, a JTAG adapter ("st-link" or some clone) and everything connected and permissions setup. Most Nucleo boards have a detachable ST-Link v2 and are cheap.1
  • Get a multiarch gdb (or a cross arm gdb and edit .cargo/config accordingly)
  • openocd -f stabilizer.cfg and leave it running
  • cargo run --release

Using USB-DFU

  • Install the DFU USB tool (dfu-util)
  • Connect to the Micro USB connector below the RJ45
  • Short JC2/BOOT
  • cargo objcopy --release --bin stabilizer -- -O binary stabilizer.bin or arm-none-eabi-objcopy -O binary target/thumbv7em-none-eabihf/release/stabilizer stabilizer.bin
  • dfu-util -a 0 -s 0x08000000:leave -D stabilizer.bin

Using ST-Link virtual mass storage

  • cargo objcopy --release --bin stabilizer -- -O binary stabilizer.bin or arm-none-eabi-objcopy -O binary target/thumbv7em-none-eabihf/release/stabilizer stabilizer.bin
  • Connect the ST-Link debugger
  • copy stabilizer.bin to the NODE_H743ZI USB disk

Protocol

Stabilizer can be configured via newline-delimited JSON over TCP. It listens on port 1235. stabilizer.py contains a reference implementation of the protocol.

  1. Build a cable: connect a standard 8 conductor ribbon with the wires numbered 1-8 to the pins on the St-Link v2 single row 2.54mm connector as 647513(82) ((i) marks an unused wire) and to the 1.27mm dual row on Stabilizer as 657483x2x1 (x marks an unused pin, enumeration is standard for dual row, as in the schematic). It's just folding the ribbon between wires 5 and 6. The signals on the ribbon are then NRST,TDI,TDO,TCK,TMS,3V3,GND,GND. ↩︎