Commit Graph

837 Commits

Author SHA1 Message Date
bors[bot] 501b3c11d3
Merge #67
67: Clippy lint r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-24 14:05:58 +00:00
Robert Jördens 8c2c0a2027 clippy: allow missing safety doc (rtfm) 2019-11-24 15:04:29 +01:00
Robert Jördens bda0ca26fb i2c/eeprom: lint 2019-11-24 14:55:20 +01:00
bors[bot] d2f8b60c27
Merge #65
65: Tim2 late enable r=jordens a=jordens

does this work for you @cjbe?

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-24 13:33:50 +00:00
Robert Jördens 1140b4fb76 board: enable TIM2 late
This was triggered by moving log_init and adding i2c_init on top of
the existing ethernet setup/init after the timer setup and enable.
Thanks @cjbe for debugging.

Also move the RCC peripheral enable calls out of i2c and eth setup.

close #55
supersedes #62
2019-11-24 14:26:27 +01:00
bors[bot] 3cf4f2690c
Merge #64
64: boards.rs: dos2unix r=jordens a=jordens

bors r+

@cjbe heads up

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-24 13:25:08 +00:00
Robert Jördens 8e84e61ff3 boards.rs: dos2unix 2019-11-24 14:15:11 +01:00
bors[bot] f3d2591e42
Merge #63
63: Default kp 1 r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-24 13:13:55 +00:00
Robert Jördens bf65b5f14a default to k_p=1 on boot 2019-11-24 13:10:01 +00:00
bors[bot] af0c9a4903
Merge #59
59: deps: bump and mainline serde-json-core r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-20 16:23:35 +00:00
Robert Jördens 712f51c015 lock: fix smoltcp 2019-11-20 17:22:44 +01:00
Robert Jördens 611043f2e2 deps: bump and mainline serde-json-core 2019-11-20 17:15:54 +01:00
bors[bot] 78f3a4884b
Merge #58
58: deps: rtfm 0.5.1 (systick and cyccntr fixes) r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-19 17:38:02 +00:00
Robert Jördens 5dfdb9014d deps: rtfm 0.5.1 (systick and cyccntr fixes) 2019-11-19 18:36:42 +01:00
bors[bot] 77dd549de9
Merge #57
57: Bump indirect r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-19 11:37:52 +00:00
Robert Jördens d141f65380 deps: bump indirect serde_derive/syn/hash32 2019-11-19 12:29:34 +01:00
Robert Jördens 2bfecd847b deps: bump rtfm indirect deps 2019-11-19 12:28:52 +01:00
bors[bot] cd6477e071
Merge #56
56: deps: rtfm release 0.5 r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-19 11:28:05 +00:00
Robert Jördens cc658a5c7b deps: rtfm release 0.5 2019-11-19 12:26:08 +01:00
bors[bot] 8045c19f53
Merge #49
49: fix memory safety issue in ethernet interface (closes #33) r=jordens a=cjbe

The CPU is allowed to implement normal memory writes out-of-order. Here
the write to the OWN flag in the DMA descriptor (normal memory) was
placed after the DMA tail pointer advance (in device memory, so not
reorderable). This meant the ethernet DMA engine stalled as it saw
a descriptor it did not own, and only restarted and sent the packet
when the next packet was released.

This fix will work as long as the CPU data cache is disabled. If we
want to enable the cache, the simplest method would be to mark SRAM3
as uncacheable via the MPU.

Co-authored-by: Chris Ballance <chris.ballance@physics.ox.ac.uk>
2019-11-16 07:26:22 +00:00
Chris Ballance ab1735950b fix memory safety issue in ethernet interface (closes #33)
The CPU is allowed to access normal memory writes out-of-order. Here
the write to the OWN flag in the DMA descriptor (normal memory) was
placed after the DMA tail pointer advance (in device memory, so not
reorderable). This meant the ethernet DMA engine stalled as it saw
a descriptor it did not own, and only restarted and sent the packet
when the next packet was released.

This fix will work as long as the CPU data cache is disabled. If we
want to enable the cache, the simplest method would be to mark SRAM3
as uncacheable via the MPU.
2019-11-16 03:25:42 +00:00
bors[bot] 53352d1281
Merge #53
53: build(deps): bump cortex-m-rtfm from v0.5.0-beta.1 to v0.5.0 r=jordens a=dependabot-preview[bot]

Bumps [cortex-m-rtfm](https://github.com/rtfm-rs/cortex-m-rtfm) from v0.5.0-beta.1 to v0.5.0.
<details>
<summary>Changelog</summary>

*Sourced from [cortex-m-rtfm's changelog](https://github.com/rtfm-rs/cortex-m-rtfm/blob/master/CHANGELOG.md).*

> ## v0.5.0 - 2019-11-14
> 
> ### Added
> 
> - Experimental support for homogeneous and heterogeneous multi-core
>   microcontrollers has been added. Support is gated behind the `homogeneous` and
>   `heterogeneous` Cargo features.
> 
> ### Changed
> 
> - [breaking-change][] [RFC 155] "explicit `Context` parameter" has been
>   implemented.
> 
> [RFC 155]: [rtfm-rs/cortex-m-rtfm#155](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/155)
> 
> - [breaking-change][] [RFC 147] "all functions must be safe" has been
>   implemented.
> 
> [RFC 147]: [rtfm-rs/cortex-m-rtfm#147](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/147)
> 
> - All the queues internally used by the framework now use `AtomicU8` indices
>   instead of `AtomicUsize`; this reduces the static memory used by the
>   framework.
> 
> - [breaking-change][] when the `capacity` argument is omitted, the capacity of
>   the task is assumed to be `1`. Before, a reasonable (but hard to predict)
>   capacity was computed based on the number of `spawn` references the task had.
> 
> - [breaking-change][] resources that are appear as exclusive references
>   (`&mut-`) no longer appear behind the `Exclusive` newtype.
> 
> - [breaking-change][] the `timer-queue` Cargo feature has been removed. The
>   `schedule` API can be used without enabling any Cargo feature.
> 
> - [breaking-change][] when the `schedule` API is used the type of
>   `init::Context.core` changes from `cortex_m::Peripherals` to
>   `rtfm::Peripherals`. The fields of `rtfm::Peripherals` do not change when
>   Cargo features are enabled.
> 
> - [breaking-change][] the monotonic timer used to implement the `schedule` API
>   is now user configurable via the `#[app(monotonic = ..)]` argument. IMPORTANT:
>   it is now the responsibility of the application author to configure and
>   initialize the chosen `monotonic` timer during the `#[init]` phase.
> 
> - [breaking-change][] the `peripherals` field is not include in `init::Context`
>   by default. One must opt-in using the `#[app(peripherals = ..)]` argument.
> 
> - [breaking-change][] the `#[exception]` and `#[interrupt]` attributes have been
>   removed. Hardware tasks are now declared using the `#[task(binds = ..)]`
>   attribute.
></tr></table> ... (truncated)
</details>
<details>
<summary>Commits</summary>

- [`6b0a2df`](6b0a2df41c) Merge [#272](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/272)
- [`4fcb6ab`](4fcb6ab7cc) v0.5.0 final release
- [`e28294b`](e28294b220) Merge [#271](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/271)
- [`2441b7e`](2441b7e389) Minor docs update to monotonic
- [`85463ed`](85463ed6c3) Merge [#268](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/268) [#270](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/270)
- [`76e2345`](76e234599f) Added struct de-structure-ing example in tips & tricks
- [`e9a8394`](e9a83947bc) fix bash comparison
- [`da9c6a7`](da9c6a714e) run cfail tests only when rustc --version == $MSRV
- [`31b392f`](31b392fe3a) CI: replace compiletest-rs with trybuild
- [`72e84cb`](72e84cb297) Merge [#266](https://github-redirect.dependabot.com/rtfm-rs/cortex-m-rtfm/issues/266)
- Additional commits viewable in [compare view](1fe9767eba...6b0a2df41c)
</details>
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2019-11-15 08:13:11 +00:00
dependabot-preview[bot] 74a31be801
build(deps): bump cortex-m-rtfm from v0.5.0-beta.1 to v0.5.0
Bumps [cortex-m-rtfm](https://github.com/rtfm-rs/cortex-m-rtfm) from v0.5.0-beta.1 to v0.5.0.
- [Release notes](https://github.com/rtfm-rs/cortex-m-rtfm/releases)
- [Changelog](https://github.com/rtfm-rs/cortex-m-rtfm/blob/master/CHANGELOG.md)
- [Commits](1fe9767eba...6b0a2df41c)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
2019-11-15 04:38:21 +00:00
Sebastien Bourdeauducq 749c42d4a7 update cargosha256 2019-11-15 11:23:21 +08:00
bors[bot] 53f2a134a1
Merge #52
52: deps: bump smoltcp and serde-json-core r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-14 15:12:44 +00:00
Robert Jördens 41a2aaf2aa deps: bump smoltcp and serde-json-core 2019-11-14 16:11:47 +01:00
Sebastien Bourdeauducq 5c89d2ba48 update cargosha256 2019-11-14 16:44:17 +08:00
bors[bot] e923dd6993
Merge #51
51: factor CPU and board-specific initialisation out of main r=jordens a=cjbe



Co-authored-by: Chris Ballance <chris.ballance@physics.ox.ac.uk>
2019-11-13 22:19:48 +00:00
Chris Ballance d7f46c1f12 factor CPU and board-specific initialisation out of main (NFC) 2019-11-13 22:13:04 +00:00
bors[bot] 4ee902027f
Merge #50
50: Fix TCP command interface rx buffer wrapping r=jordens a=dnadlinger

Previously, if a message spanned the end of the
receive ring buffer, the last byte in the buffer
would be missing from the to-be-decoded message,
leading to a parse error or panic.

With this commit, >3M commands were exchanged
over one socket without further issues.

Co-authored-by: David Nadlinger <code@klickverbot.at>
2019-11-13 09:57:02 +00:00
David Nadlinger 2297286360 Fix TCP command interface rx buffer wrapping
Previously, if a message spanned the end of the
receive ring buffer, the last byte in the buffer
would be missing from the to-be-decoded message,
leading to a parse error or panic.

With this commit, >3M commands were exchanged
over one socket without further issues.
2019-11-13 01:50:18 +00:00
bors[bot] bc85cd478b
Merge #44
44: build(deps): bump serde from 1.0.101 to 1.0.102 r=jordens a=dependabot-preview[bot]

Bumps [serde](https://github.com/serde-rs/serde) from 1.0.101 to 1.0.102.
<details>
<summary>Release notes</summary>

*Sourced from [serde's releases](https://github.com/serde-rs/serde/releases).*

> ## v1.0.102
> - Support deserializing `PathBuf` from bytes like `&Path` already did, and support deserializing `Box<Path>` ([#1656](https://github-redirect.dependabot.com/serde-rs/serde/issues/1656), thanks [@&#8203;heftig](https://github.com/heftig))
</details>
<details>
<summary>Commits</summary>

- [`2ceabad`](2ceabad360) Release 1.0.102
- [`a00aee1`](a00aee1495) Use a dedicated cfg for PathBuf::into_boxed_path
- [`4e31c99`](4e31c9984d) Merge pull request [#1656](https://github-redirect.dependabot.com/serde-rs/serde/issues/1656) from heftig/path-improvements
- [`b8772a1`](b8772a1e40) Deserialize Box\<Path> through PathBuf::into_boxed_path
- [`42990d8`](42990d8264) Deserialize PathBuf from bytes
- [`cf31418`](cf31418555) Resolve unused_self lint
- [`5db72b8`](5db72b8ad9) Ignore must_use_candidate pedantic lint
- [`fe8f8bc`](fe8f8bcf7b) Address needless_doctest_main lint in serde_test
- [`d4d737d`](d4d737de8d) Resolve redundant_clone lint
- [`52f6e96`](52f6e96ee8) Ignore needless_doctest_main lint
- Additional commits viewable in [compare view](https://github.com/serde-rs/serde/compare/v1.0.101...v1.0.102)
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2019-11-11 11:58:56 +00:00
bors[bot] 39cb1afcfd
Merge #48
48: remove unused code, deny warnings r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-11 11:20:53 +00:00
dependabot-preview[bot] 34ddcf1a90
build(deps): bump serde from 1.0.101 to 1.0.102
Bumps [serde](https://github.com/serde-rs/serde) from 1.0.101 to 1.0.102.
- [Release notes](https://github.com/serde-rs/serde/releases)
- [Commits](https://github.com/serde-rs/serde/compare/v1.0.101...v1.0.102)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
2019-11-11 11:15:32 +00:00
Robert Jördens 0b4f7c9201 remove unused code, deny warnings 2019-11-11 12:04:50 +01:00
bors[bot] 0cb1643779
Merge #45
45: build(deps): bump stm32h7 from 0.8.0 to 0.9.0 r=jordens a=dependabot-preview[bot]

Bumps [stm32h7](https://github.com/stm32-rs/stm32-rs) from 0.8.0 to 0.9.0.
<details>
<summary>Changelog</summary>

*Sourced from [stm32h7's changelog](https://github.com/stm32-rs/stm32-rs/blob/master/CHANGELOG.md).*

> ## [v0.9.0] 2019-11-10
> 
> Family-specific:
> 
> * F1:
>     * F100 ADC ([#270](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/270))
> * F3:
>     * ADC, COMP, DAC, HRTIM, OPAMP ([#287](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/287))
>     * HRTIM interrupt numbers ([#289](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/289))
>     * Update README concerning parts in each module ([#295](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/295))
> * F4:
>     * F401 and F411 USB OTG FS patch ([#272](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/272))
> * F7:
>     * Update SVD files to latest from vendor ([#299](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/299))
> * L0:
>     * L0xx: NVIC priority bits ([#275](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/275))
>     * L0xx: fixes ([#291](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/291), [#292](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/292), [#293](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/293))
>     * L0x1: RCC APB1ENR TIM3 fix ([#297](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/297))
>     * L0xx: SYSCFG CFGR3 fixes ([#300](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/300))
> * H7:
>     * Add dual core parts ([#276](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/276), [#285](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/285))
>     * Correct PLL2DIVR names ([#281](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/281))
>     * Split ethernet peripheral in dual core parts ([#288](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/288))
> * G0:
>     * Update G0 SVD files ([#286](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/286))
> * G4:
>     * RCC fixes ([#294](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/294))
> 
> Common:
> 
> * OTG HS patches ([#272](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/272), [#274](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/274))
> * Updated to svd2rust 0.16.1 ([#271](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/271), [#283](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/283))
> * Explicitly open YAML files in UTF-8 ([#277](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/277))
> * Makefile improvements ([#278](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/278), [#279](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/279), [#280](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/280))
> * svdpatch supports copying peripherals from another SVD ([#298](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/298))
> 
> Thanks to:
> 
> [@&#8203;burrbull] [@&#8203;disasm] [@&#8203;albru123] [@&#8203;kitzin] [@&#8203;richardeoin] [@&#8203;dotcypress]
> [@&#8203;richard7770] [@&#8203;jonas-schievink] [@&#8203;ajfrantz] [@&#8203;aurelj] [@&#8203;osannolik] [@&#8203;rfuest]
</details>
<details>
<summary>Commits</summary>

- [`5d2c088`](5d2c08864c) v0.9.0
- [`523683b`](523683b06a) Merge [#298](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/298)
- [`2894624`](28946241ff) Merge [#299](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/299)
- [`bc4467b`](bc4467b94a) Update stm32_part_table.yaml for STM32F7x5
- [`c04f809`](c04f809cdc) Merge [#300](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/300)
- [`a82df3a`](a82df3abad) Mark REF_LOCK as read-write
- [`8b5eb0a`](8b5eb0a5cb) Fix SYSCFG CFGR3 register fields
- [`b33a2f0`](b33a2f02a4) Rename conflicting LCD-TFT interrupts
- [`76be6f7`](76be6f7d3b) Split stm32f7x5 feature into stm32f745 and stm32f765
- [`7589009`](758900938c) Update devices for new SVD files
- Additional commits viewable in [compare view](https://github.com/stm32-rs/stm32-rs/compare/v0.8.0...v0.9.0)
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</details>

Co-authored-by: dependabot-preview[bot] <27856297+dependabot-preview[bot]@users.noreply.github.com>
Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-11 10:56:05 +00:00
Robert Jördens 65cf0c1594 rcc: pac 0.9 renames 2019-11-11 11:46:07 +01:00
bors[bot] c52172f753
Merge #47
47: Travis nightly r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-11 10:42:52 +00:00
Robert Jördens 404ece616a travis: try nightly as well 2019-11-11 11:31:39 +01:00
bors[bot] 5a86aca3ef
Merge #46
46: travis: stable r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-11 10:31:27 +00:00
Robert Jördens f11e33921f travis: stable 2019-11-11 11:30:41 +01:00
dependabot-preview[bot] 305bb0397b
build(deps): bump stm32h7 from 0.8.0 to 0.9.0
Bumps [stm32h7](https://github.com/stm32-rs/stm32-rs) from 0.8.0 to 0.9.0.
- [Release notes](https://github.com/stm32-rs/stm32-rs/releases)
- [Changelog](https://github.com/stm32-rs/stm32-rs/blob/master/CHANGELOG.md)
- [Commits](https://github.com/stm32-rs/stm32-rs/compare/v0.8.0...v0.9.0)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
2019-11-11 04:33:07 +00:00
Sebastien Bourdeauducq 2aaa47ced1 add cargosha256.nix 2019-11-01 10:10:19 +08:00
bors[bot] 7970508de2
Merge #43
43: Stable rust r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-10-22 13:49:52 +00:00
Robert Jördens 1a669909aa deps: bump 2019-10-22 13:47:19 +00:00
Robert Jördens 07cbf61b23 rtfm: v0.5.0-beta.1 2019-10-22 13:44:40 +00:00
Robert Jördens 4c205f1a93 openocd.gdb: modern gdb is stricter 2019-10-22 13:44:04 +00:00
Robert Jördens 17012621dd use stable rust (1.38.0) 2019-10-22 13:43:49 +00:00
bors[bot] 1b846c6d19
Merge #42
42: Bump deps r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-10-13 12:36:01 +00:00
Robert Jördens 7e366f08ea dependencies: bump indirect 2019-10-13 14:34:54 +02:00