45: build(deps): bump stm32h7 from 0.8.0 to 0.9.0 r=jordens a=dependabot-preview[bot]

Bumps [stm32h7](https://github.com/stm32-rs/stm32-rs) from 0.8.0 to 0.9.0.
<details>
<summary>Changelog</summary>

*Sourced from [stm32h7's changelog](https://github.com/stm32-rs/stm32-rs/blob/master/CHANGELOG.md).*

> ## [v0.9.0] 2019-11-10
> 
> Family-specific:
> 
> * F1:
>     * F100 ADC ([#270](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/270))
> * F3:
>     * ADC, COMP, DAC, HRTIM, OPAMP ([#287](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/287))
>     * HRTIM interrupt numbers ([#289](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/289))
>     * Update README concerning parts in each module ([#295](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/295))
> * F4:
>     * F401 and F411 USB OTG FS patch ([#272](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/272))
> * F7:
>     * Update SVD files to latest from vendor ([#299](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/299))
> * L0:
>     * L0xx: NVIC priority bits ([#275](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/275))
>     * L0xx: fixes ([#291](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/291), [#292](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/292), [#293](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/293))
>     * L0x1: RCC APB1ENR TIM3 fix ([#297](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/297))
>     * L0xx: SYSCFG CFGR3 fixes ([#300](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/300))
> * H7:
>     * Add dual core parts ([#276](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/276), [#285](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/285))
>     * Correct PLL2DIVR names ([#281](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/281))
>     * Split ethernet peripheral in dual core parts ([#288](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/288))
> * G0:
>     * Update G0 SVD files ([#286](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/286))
> * G4:
>     * RCC fixes ([#294](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/294))
> 
> Common:
> 
> * OTG HS patches ([#272](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/272), [#274](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/274))
> * Updated to svd2rust 0.16.1 ([#271](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/271), [#283](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/283))
> * Explicitly open YAML files in UTF-8 ([#277](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/277))
> * Makefile improvements ([#278](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/278), [#279](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/279), [#280](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/280))
> * svdpatch supports copying peripherals from another SVD ([#298](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/298))
> 
> Thanks to:
> 
> [@&#8203;burrbull] [@&#8203;disasm] [@&#8203;albru123] [@&#8203;kitzin] [@&#8203;richardeoin] [@&#8203;dotcypress]
> [@&#8203;richard7770] [@&#8203;jonas-schievink] [@&#8203;ajfrantz] [@&#8203;aurelj] [@&#8203;osannolik] [@&#8203;rfuest]
</details>
<details>
<summary>Commits</summary>

- [`5d2c088`](5d2c08864c) v0.9.0
- [`523683b`](523683b06a) Merge [#298](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/298)
- [`2894624`](28946241ff) Merge [#299](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/299)
- [`bc4467b`](bc4467b94a) Update stm32_part_table.yaml for STM32F7x5
- [`c04f809`](c04f809cdc) Merge [#300](https://github-redirect.dependabot.com/stm32-rs/stm32-rs/issues/300)
- [`a82df3a`](a82df3abad) Mark REF_LOCK as read-write
- [`8b5eb0a`](8b5eb0a5cb) Fix SYSCFG CFGR3 register fields
- [`b33a2f0`](b33a2f02a4) Rename conflicting LCD-TFT interrupts
- [`76be6f7`](76be6f7d3b) Split stm32f7x5 feature into stm32f745 and stm32f765
- [`7589009`](758900938c) Update devices for new SVD files
- Additional commits viewable in [compare view](https://github.com/stm32-rs/stm32-rs/compare/v0.8.0...v0.9.0)
</details>
<br />

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</details>

Co-authored-by: dependabot-preview[bot] <27856297+dependabot-preview[bot]@users.noreply.github.com>
Co-authored-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
bors[bot] 2019-11-11 10:56:05 +00:00 committed by GitHub
commit 0cb1643779
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 7 additions and 7 deletions

6
Cargo.lock generated
View File

@ -331,7 +331,7 @@ dependencies = [
"serde 1.0.101 (registry+https://github.com/rust-lang/crates.io-index)",
"serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)",
"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=0fedb1d)",
"stm32h7 0.8.0 (registry+https://github.com/rust-lang/crates.io-index)",
"stm32h7 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]]
@ -341,7 +341,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
[[package]]
name = "stm32h7"
version = "0.8.0"
version = "0.9.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
dependencies = [
"bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)",
@ -440,7 +440,7 @@ dependencies = [
"checksum serde_derive 1.0.101 (registry+https://github.com/rust-lang/crates.io-index)" = "4b133a43a1ecd55d4086bd5b4dc6c1751c68b1bfbeba7a5040442022c7e7c02e"
"checksum smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=0fedb1d)" = "<none>"
"checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
"checksum stm32h7 0.8.0 (registry+https://github.com/rust-lang/crates.io-index)" = "63001af508d3332bd2dd81d4212b69e10f45e8f5435b7dab5def36178b9c1c17"
"checksum stm32h7 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "6fd678579307324f1890552fe644331ce0a46607f2466aac8609f782d9b26524"
"checksum syn 0.15.44 (registry+https://github.com/rust-lang/crates.io-index)" = "9ca4b3b69a77cbe1ffc9e198781b7acb0c7365a883670e8f1c1bc66fba79a5c5"
"checksum syn 1.0.5 (registry+https://github.com/rust-lang/crates.io-index)" = "66850e97125af79138385e9b88339cbcd037e3f28ceab8c5ad98e64f0f1f80bf"
"checksum typenum 1.11.2 (registry+https://github.com/rust-lang/crates.io-index)" = "6d2783fe2d6b8c1101136184eb41be8b1ad379e4657050b8aaff0c79ee7575f9"

View File

@ -42,7 +42,7 @@ git = "https://github.com/quartiq/serde-json-core.git"
rev = "fc764de"
[dependencies.stm32h7]
version = "0.8"
version = "0.9"
features = ["stm32h743", "rt"]
[dependencies.smoltcp]

View File

@ -149,9 +149,9 @@ fn rcc_pll_setup(rcc: &pac::RCC, flash: &pac::FLASH) {
// Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz
rcc.pll2divr.write(|w| unsafe {
w.divn1().bits(25 - 1) // feebdack divider
.divp1().bits(2 - 1) // p output divider
.divq1().bits(2 - 1) // q output divider
w.divn2().bits(25 - 1) // feebdack divider
.divp2().bits(2 - 1) // p output divider
.divq2().bits(2 - 1) // q output divider
});
rcc.cr.modify(|_, w| w.pll2on().on());
while !rcc.cr.read().pll2rdy().is_ready() {}