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* rtfm: (21 commits)
  cargo: bump stm32h7, misc
  cargo: update
  panic: abort, not halt
  fix panic handler
  panic: turn red leds on
  bump heapless
  gpio: use odr variants
  parametrize poll return
  make json poll generic
  cargo: update
  rtfm: command port
  rtfm: status port
  rtfm: move ethernet into idle
  rtfm: continue work
  use rtfm [wip]
  ethernet peripheral ownership, cs
  pac: rcc
  pac updates (~0.8)
  stm32h7 svd and pac changes
  new stm32h7 pac
  ...
This commit is contained in:
Robert Jördens 2019-08-06 14:37:12 +02:00
commit 52e59b69c2
4 changed files with 789 additions and 768 deletions
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161
Cargo.lock generated
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"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f" "checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
"checksum rand 0.5.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c618c47cd3ebd209790115ab837de41425723956ad3ce2e6a7f09890947cacb9" "checksum rand 0.5.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c618c47cd3ebd209790115ab837de41425723956ad3ce2e6a7f09890947cacb9"
"checksum rand_core 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "7a6fdeb83b075e8266dcc8762c22776f6877a63111121f5f8c7411e5be7eed4b" "checksum rand_core 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "7a6fdeb83b075e8266dcc8762c22776f6877a63111121f5f8c7411e5be7eed4b"
@ -344,13 +379,13 @@ dependencies = [
"checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a" "checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
"checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403" "checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403"
"checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" "checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
"checksum serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "a72e9b96fa45ce22a4bc23da3858dfccfd60acd28a25bcd328a98fdd6bea43fd" "checksum serde 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "7fe5626ac617da2f2d9c48af5515a21d5a480dbd151e01bb1c355e26a3e68113"
"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)" = "<none>" "checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)" = "<none>"
"checksum serde_derive 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "101b495b109a3e3ca8c4cbe44cf62391527cdfb6ba15821c5ce80bcd5ea23f9f" "checksum serde_derive 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "01e69e1b8a631f245467ee275b8c757b818653c6d704cdbcaeb56b56767b529c"
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19
Cargo.toml
View File

@ -30,25 +30,32 @@ default-target = "thumbv7em-none-eabihf"
cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] } cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] }
cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-rt = { version = "0.6", features = ["device"] }
cortex-m-log = { version = "0.5", features = ["log-integration"] } cortex-m-log = { version = "0.5", features = ["log-integration"] }
stm32h7 = { version = "0.7", features = ["stm32h7x3", "rt"] }
log = "0.4" log = "0.4"
panic-abort = "0.3" panic-semihosting = { version = "0.5", optional = true }
panic-semihosting = { version = "0.5.2", optional = true }
serde = { version = "1.0", features = ["derive"], default-features = false } serde = { version = "1.0", features = ["derive"], default-features = false }
heapless = { version = "0.4" } heapless = { version = "0.5" }
[dependencies.serde-json-core] [dependencies.serde-json-core]
# version = "0.0" # version = "0.0"
git = "https://github.com/quartiq/serde-json-core.git" git = "https://github.com/quartiq/serde-json-core.git"
rev = "82fdca9" rev = "fc764de"
[dependencies.stm32h7]
version = "0.8"
features = ["stm32h743", "rt"]
[dependencies.smoltcp] [dependencies.smoltcp]
#git = "https://github.com/m-labs/smoltcp.git" #git = "https://github.com/m-labs/smoltcp.git"
#rev = "cd893e6" #rev = "0f61443"
version = "0.5" version = "0.5"
features = ["proto-ipv4", "socket-tcp"] features = ["proto-ipv4", "socket-tcp"]
default-features = false default-features = false
[dependencies.cortex-m-rtfm]
git = "https://github.com/japaric/cortex-m-rtfm"
rev = "fafeeb2"
features = ["timer-queue"]
[features] [features]
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
bkpt = [ ] bkpt = [ ]

138
src/eth.rs
View File

@ -1,6 +1,5 @@
use core::{slice, cmp}; use core::{slice, cmp};
use cortex_m; use stm32h7::stm32h743 as pac;
use stm32h7::stm32h7x3 as stm32;
use smoltcp::Result; use smoltcp::Result;
use smoltcp::time::Instant; use smoltcp::time::Instant;
use smoltcp::wire::EthernetAddress; use smoltcp::wire::EthernetAddress;
@ -87,7 +86,7 @@ use self::cr_consts::*;
const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102; const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) { pub fn setup(rcc: &pac::RCC, syscfg: &pac::SYSCFG) {
rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
rcc.ahb1enr.modify(|_, w| { rcc.ahb1enr.modify(|_, w| {
w.eth1macen().set_bit() w.eth1macen().set_bit()
@ -99,8 +98,8 @@ pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) {
//rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit()); //rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit());
} }
pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB,
gpioc: &stm32::GPIOC, gpiog: &stm32::GPIOG) { gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) {
// PA1 RMII_REF_CLK // PA1 RMII_REF_CLK
gpioa.moder.modify(|_, w| w.moder1().alternate()); gpioa.moder.modify(|_, w| w.moder1().alternate());
gpioa.afrl.modify(|_, w| w.afr1().af11()); gpioa.afrl.modify(|_, w| w.afr1().af11());
@ -141,10 +140,7 @@ pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB,
const PHY_ADDR: u8 = 0; const PHY_ADDR: u8 = 0;
fn phy_read(reg_addr: u8) -> u16 { fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 {
cortex_m::interrupt::free(|_cs| {
let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() };
while mac.macmdioar.read().mb().bit_is_set() {} while mac.macmdioar.read().mb().bit_is_set() {}
mac.macmdioar.modify(|_, w| unsafe { mac.macmdioar.modify(|_, w| unsafe {
w w
@ -156,13 +152,9 @@ fn phy_read(reg_addr: u8) -> u16 {
}); });
while mac.macmdioar.read().mb().bit_is_set() {} while mac.macmdioar.read().mb().bit_is_set() {}
mac.macmdiodr.read().md().bits() mac.macmdiodr.read().md().bits()
})
} }
fn phy_write(reg_addr: u8, reg_data: u16) { fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) {
cortex_m::interrupt::free(|_cs| {
let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() };
while mac.macmdioar.read().mb().bit_is_set() {} while mac.macmdioar.read().mb().bit_is_set() {}
mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) });
mac.macmdioar.modify(|_, w| unsafe { mac.macmdioar.modify(|_, w| unsafe {
@ -174,15 +166,14 @@ fn phy_write(reg_addr: u8, reg_data: u16) {
.mb().set_bit() .mb().set_bit()
}); });
while mac.macmdioar.read().mb().bit_is_set() {} while mac.macmdioar.read().mb().bit_is_set() {}
})
} }
// Writes a value to an extended PHY register in MMD address space // Writes a value to an extended PHY register in MMD address space
fn phy_write_ext(reg_addr: u16, reg_data: u16) { fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) {
phy_write(PHY_REG_CTL, 0x0003); // set address phy_write(PHY_REG_CTL, 0x0003, mac); // set address
phy_write(PHY_REG_ADDAR, reg_addr); phy_write(PHY_REG_ADDAR, reg_addr, mac);
phy_write(PHY_REG_CTL, 0x4003); // set data phy_write(PHY_REG_CTL, 0x4003, mac); // set data
phy_write(PHY_REG_ADDAR, reg_data); phy_write(PHY_REG_ADDAR, reg_data, mac);
} }
#[repr(align(4))] #[repr(align(4))]
@ -201,7 +192,7 @@ impl RxRing {
} }
} }
fn init(&mut self) { unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.desc_buf[0].len() % 4, 0);
assert_eq!(self.pkt_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0);
@ -214,17 +205,10 @@ impl RxRing {
} }
} }
cortex_m::interrupt::free(|_cs| unsafe { let addr = &self.desc_buf as *const _ as u32;
let dma = &*stm32::ETHERNET_DMA::ptr(); assert_eq!(addr & 0x3, 0);
dma.dmacrx_dlar.write(|w| w.bits(addr));
dma.dmacrx_dlar.write(|w| { dma.dmacrx_rlr.write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1));
w.bits(&self.desc_buf as *const _ as u32)
});
dma.dmacrx_rlr.write(|w| {
w.rdrl().bits(self.desc_buf.len() as u16 - 1)
});
});
self.cur_desc = 0; self.cur_desc = 0;
for _ in 0..self.desc_buf.len() { for _ in 0..self.desc_buf.len() {
@ -259,11 +243,10 @@ impl RxRing {
self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP; self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP;
self.desc_buf[self.cur_desc][3] = EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN; self.desc_buf[self.cur_desc][3] = EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN;
let addr = &self.desc_buf[self.cur_desc] as *const _; let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
cortex_m::interrupt::free(|_cs| { assert_eq!(addr & 0x3, 0);
let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() }; let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr as u32) }); dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) });
});
self.cur_desc = self.next_desc(); self.cur_desc = self.next_desc();
} }
@ -285,7 +268,7 @@ impl TxRing {
} }
} }
fn init(&mut self) { unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.desc_buf[0].len() % 4, 0);
assert_eq!(self.pkt_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0);
@ -299,21 +282,13 @@ impl TxRing {
} }
self.cur_desc = 0; self.cur_desc = 0;
cortex_m::interrupt::free(|_cs| unsafe { let addr = &self.desc_buf as *const _ as u32;
let dma = &*stm32::ETHERNET_DMA::ptr(); assert_eq!(addr & 0x3, 0);
dma.dmactx_dlar.write(|w| w.bits(addr));
dma.dmactx_dlar.write(|w| { dma.dmactx_rlr.write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1));
w.bits(&self.desc_buf as *const _ as u32) let addr = &self.desc_buf[0] as *const _ as u32;
}); assert_eq!(addr & 0x3, 0);
dma.dmactx_dtpr.write(|w| w.bits(addr));
dma.dmactx_rlr.write(|w| {
w.tdrl().bits(self.desc_buf.len() as u16 - 1)
});
dma.dmactx_dtpr.write(|w| {
w.bits(&self.desc_buf[0] as *const _ as u32)
});
});
} }
fn next_desc(&self) -> usize { fn next_desc(&self) -> usize {
@ -337,11 +312,10 @@ impl TxRing {
self.desc_buf[self.cur_desc][3] = EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD; self.desc_buf[self.cur_desc][3] = EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD;
self.cur_desc = self.next_desc(); self.cur_desc = self.next_desc();
let addr = &self.desc_buf[self.cur_desc] as *const _; let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
cortex_m::interrupt::free(|_cs| { assert_eq!(addr & 0x3, 0);
let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() }; let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr as u32) }); dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) });
});
} }
} }
@ -356,13 +330,11 @@ impl Device {
} }
// After `init` is called, `Device` shall not be moved. // After `init` is called, `Device` shall not be moved.
pub unsafe fn init(&mut self, mac: EthernetAddress) { pub unsafe fn init(&mut self, mac: EthernetAddress,
cortex_m::interrupt::free(|_cs| { eth_mac: &pac::ETHERNET_MAC,
let eth_mac = &*stm32::ETHERNET_MAC::ptr(); eth_dma: &pac::ETHERNET_DMA,
let eth_dma = &*stm32::ETHERNET_DMA::ptr(); eth_mtl: &pac::ETHERNET_MTL,
let _eth_mmc = &*stm32::ETHERNET_MMC::ptr(); ) {
let eth_mtl = &*stm32::ETHERNET_MTL::ptr();
eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
while eth_dma.dmamr.read().swr().bit_is_set() {} while eth_dma.dmamr.read().swr().bit_is_set() {}
@ -407,9 +379,6 @@ impl Device {
eth_mac.maca0hr.write(|w| eth_mac.maca0hr.write(|w|
w.addrhi().bits( u16::from(mac.0[4]) | w.addrhi().bits( u16::from(mac.0[4]) |
(u16::from(mac.0[5]) << 8)) (u16::from(mac.0[5]) << 8))
.ae().set_bit()
//.sa().clear_bit()
//.mbc().bits(0b000000)
); );
// frame filter register // frame filter register
eth_mac.macpfr.modify(|_, w| { eth_mac.macpfr.modify(|_, w| {
@ -433,12 +402,12 @@ impl Device {
}); });
eth_mac.macwtr.write(|w| w.pwe().clear_bit()); eth_mac.macwtr.write(|w| w.pwe().clear_bit());
// Flow Control Register // Flow Control Register
eth_mac.macqtxfcr.modify(|_, w| { eth_mac.macqtx_fcr.modify(|_, w| {
// Pause time // Pause time
w.pt().bits(0x100) w.pt().bits(0x100)
}); });
eth_mac.macrxfcr.modify(|_, w| w); eth_mac.macrx_fcr.modify(|_, w| w);
eth_mtl.mtlrxqomr.modify(|_, w| eth_mtl.mtlrx_qomr.modify(|_, w|
w w
// Receive store and forward // Receive store and forward
.rsf().set_bit() .rsf().set_bit()
@ -449,20 +418,20 @@ impl Device {
// Forward undersized good packets // Forward undersized good packets
.fup().clear_bit() .fup().clear_bit()
); );
eth_mtl.mtltxqomr.modify(|_, w| { eth_mtl.mtltx_qomr.modify(|_, w| {
w w
// Transmit store and forward // Transmit store and forward
.tsf().set_bit() .tsf().set_bit()
}); });
if (phy_read(PHY_REG_ID1) != 0x0007) | (phy_read(PHY_REG_ID2) != 0xC131) { if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007) | (phy_read(PHY_REG_ID2, eth_mac) != 0xC131) {
error!("PHY ID error!"); error!("PHY ID error!");
} }
phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET); phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac);
while phy_read(PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}; while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {};
phy_write_ext(PHY_REG_WUCSR, 0); phy_write_ext(PHY_REG_WUCSR, 0, eth_mac);
phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M); phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M, eth_mac);
/* /*
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {}; while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {};
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {}; while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {};
@ -473,7 +442,7 @@ impl Device {
// operation mode register // operation mode register
eth_dma.dmamr.modify(|_, w| { eth_dma.dmamr.modify(|_, w| {
w w
.intm().clear_bit() // FIXME: bits(0b00) .intm().bits(0b00)
// Rx Tx priority ratio 1:1 // Rx Tx priority ratio 1:1
.pr().bits(0b000) .pr().bits(0b000)
.txpr().clear_bit() .txpr().clear_bit()
@ -511,15 +480,15 @@ impl Device {
.rpf().clear_bit() .rpf().clear_bit()
}); });
self.rx.init(); self.rx.init(eth_dma);
self.tx.init(); self.tx.init(eth_dma);
// Manage MAC transmission and reception // Manage MAC transmission and reception
eth_mac.maccr.modify(|_, w| { eth_mac.maccr.modify(|_, w| {
w.re().bit(true) // Receiver Enable w.re().bit(true) // Receiver Enable
.te().bit(true) // Transmiter Enable .te().bit(true) // Transmiter Enable
}); });
eth_mtl.mtltxqomr.modify(|_, w| w.ftq().set_bit()); eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit());
// Manage DMA transmission and reception // Manage DMA transmission and reception
eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());
@ -529,7 +498,6 @@ impl Device {
w.tps().set_bit() w.tps().set_bit()
.rps().set_bit() .rps().set_bit()
); );
});
} }
} }
@ -590,8 +558,7 @@ impl<'a> phy::TxToken for TxToken<'a> {
} }
} }
pub unsafe fn interrupt_handler() { pub unsafe fn interrupt_handler(eth_dma: &pac::ETHERNET_DMA) {
let eth_dma = &*stm32::ETHERNET_DMA::ptr();
eth_dma.dmacsr.write(|w| eth_dma.dmacsr.write(|w|
w w
.nis().set_bit() .nis().set_bit()
@ -600,8 +567,7 @@ pub unsafe fn interrupt_handler() {
); );
} }
pub unsafe fn enable_interrupt() { pub unsafe fn enable_interrupt(eth_dma: &pac::ETHERNET_DMA) {
let eth_dma = &*stm32::ETHERNET_DMA::ptr();
eth_dma.dmacier.modify(|_, w| eth_dma.dmacier.modify(|_, w|
w w
.nie().set_bit() .nie().set_bit()

713
src/main.rs
View File

@ -3,9 +3,17 @@
#![feature(asm)] #![feature(asm)]
// Enable returning `!` // Enable returning `!`
#![feature(never_type)] #![feature(never_type)]
#![feature(core_intrinsics)]
#[inline(never)]
#[panic_handler]
#[cfg(not(feature = "semihosting"))] #[cfg(not(feature = "semihosting"))]
extern crate panic_abort; fn panic(_info: &core::panic::PanicInfo) -> ! {
let gpiod = unsafe { &*pac::GPIOD::ptr() };
gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
unsafe { core::intrinsics::abort(); }
}
#[cfg(feature = "semihosting")] #[cfg(feature = "semihosting")]
extern crate panic_semihosting; extern crate panic_semihosting;
@ -13,17 +21,15 @@ extern crate panic_semihosting;
extern crate log; extern crate log;
use core::ptr; use core::ptr;
use core::cell::RefCell; // use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
use core::fmt::Write; use core::fmt::Write;
use cortex_m_rt::{entry, exception}; use cortex_m_rt::exception;
use stm32h7::stm32h7x3::{self as stm32, Peripherals, CorePeripherals, interrupt}; use stm32h7::stm32h743 as pac;
use cortex_m::interrupt::Mutex;
use heapless::{String, Vec, consts::*}; use heapless::{String, Vec, consts::*};
use smoltcp as net; use smoltcp as net;
use serde::{Serialize, Deserialize}; use serde::{Serialize, Deserialize, de::DeserializeOwned};
use serde_json_core::{ser::to_string, de::from_slice}; use serde_json_core::{ser::to_string, de::from_slice};
mod eth; mod eth;
@ -37,7 +43,7 @@ fn init_log() {}
#[cfg(feature = "semihosting")] #[cfg(feature = "semihosting")]
fn init_log() { fn init_log() {
use log::LevelFilter; use log::LevelFilter;
use cortex_m_log::log::{Logger, init}; use cortex_m_log::log::{Logger, init as init_log};
use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout}; use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout};
static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None; static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
let logger = Logger { let logger = Logger {
@ -48,7 +54,7 @@ fn init_log() {
LOGGER.get_or_insert(logger) LOGGER.get_or_insert(logger)
}; };
init(logger).unwrap(); init_log(logger).unwrap();
} }
// Pull in build information (from `built` crate) // Pull in build information (from `built` crate)
@ -57,10 +63,10 @@ mod build_info {
// include!(concat!(env!("OUT_DIR"), "/built.rs")); // include!(concat!(env!("OUT_DIR"), "/built.rs"));
} }
fn pwr_setup(pwr: &stm32::PWR) { fn pwr_setup(pwr: &pac::PWR) {
// go to VOS1 voltage scale for high perf // go to VOS1 voltage scale for high perf
pwr.cr3.write(|w| pwr.cr3.write(|w|
w.sden().set_bit() w.scuen().set_bit()
.ldoen().set_bit() .ldoen().set_bit()
.bypass().clear_bit() .bypass().clear_bit()
); );
@ -69,7 +75,7 @@ fn pwr_setup(pwr: &stm32::PWR) {
while pwr.d3cr.read().vosrdy().bit_is_clear() {} while pwr.d3cr.read().vosrdy().bit_is_clear() {}
} }
fn rcc_reset(rcc: &stm32::RCC) { fn rcc_reset(rcc: &pac::RCC) {
// Reset all peripherals // Reset all peripherals
rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
rcc.ahb1rstr.write(|w| unsafe { w.bits(0)}); rcc.ahb1rstr.write(|w| unsafe { w.bits(0)});
@ -95,48 +101,44 @@ fn rcc_reset(rcc: &stm32::RCC) {
rcc.apb4rstr.write(|w| unsafe { w.bits(0)}); rcc.apb4rstr.write(|w| unsafe { w.bits(0)});
} }
fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { fn rcc_pll_setup(rcc: &pac::RCC, flash: &pac::FLASH) {
// Ensure HSI is on and stable // Switch to HSI to mess with HSE
rcc.cr.modify(|_, w| w.hsion().set_bit()); rcc.cr.modify(|_, w| w.hsion().on());
while rcc.cr.read().hsirdy().bit_is_clear() {} while rcc.cr.read().hsirdy().is_not_ready() {}
rcc.cfgr.modify(|_, w| w.sw().hsi());
// Set system clock to HSI while !rcc.cfgr.read().sws().is_hsi() {}
rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0) }); // hsi rcc.cr.write(|w| w.hsion().on());
while rcc.cfgr.read().sws().bits() != 0 {}
// Clear registers to reset value
rcc.cr.write(|w| w.hsion().set_bit());
rcc.cfgr.reset(); rcc.cfgr.reset();
// Ensure HSE is on and stable // Ensure HSE is on and stable
rcc.cr.modify(|_, w| rcc.cr.modify(|_, w|
w.hseon().set_bit() w.hseon().on()
.hsebyp().clear_bit()); .hsebyp().not_bypassed());
while rcc.cr.read().hserdy().bit_is_clear() {} while !rcc.cr.read().hserdy().is_ready() {}
rcc.pllckselr.modify(|_, w| unsafe { rcc.pllckselr.modify(|_, w|
w.pllsrc().bits(0b10) // hse w.pllsrc().hse()
.divm1().bits(1) // ref prescaler .divm1().bits(1) // ref prescaler
.divm2().bits(1) // ref prescaler .divm2().bits(1) // ref prescaler
}); );
// Configure PLL1: 8MHz /1 *100 /2 = 400 MHz // Configure PLL1: 8MHz /1 *100 /2 = 400 MHz
rcc.pllcfgr.modify(|_, w| unsafe { rcc.pllcfgr.modify(|_, w|
w.pll1vcosel().clear_bit() // 192-836 MHz VCO w.pll1vcosel().wide_vco() // 192-836 MHz VCO
.pll1rge().bits(0b11) // 8-16 MHz PFD .pll1rge().range8() // 8-16 MHz PFD
.pll1fracen().clear_bit() .pll1fracen().reset()
.divp1en().set_bit() .divp1en().enabled()
.pll2vcosel().set_bit() // 150-420 MHz VCO .pll2vcosel().medium_vco() // 150-420 MHz VCO
.pll2rge().bits(0b11) // 8-16 MHz PFD .pll2rge().range8() // 8-16 MHz PFD
.pll2fracen().clear_bit() .pll2fracen().reset()
.divp2en().set_bit() .divp2en().enabled()
.divq2en().set_bit() .divq2en().enabled()
}); );
rcc.pll1divr.write(|w| unsafe { rcc.pll1divr.write(|w| unsafe {
w.divn1().bits(100 - 1) // feebdack divider w.divn1().bits(100 - 1) // feebdack divider
.divp1().bits(2 - 1) // p output divider .divp1().div2() // p output divider
}); });
rcc.cr.modify(|_, w| w.pll1on().set_bit()); rcc.cr.modify(|_, w| w.pll1on().on());
while rcc.cr.read().pll1rdy().bit_is_clear() {} while !rcc.cr.read().pll1rdy().is_ready() {}
// Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz // Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz
rcc.pll2divr.write(|w| unsafe { rcc.pll2divr.write(|w| unsafe {
@ -144,24 +146,22 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
.divp1().bits(2 - 1) // p output divider .divp1().bits(2 - 1) // p output divider
.divq1().bits(2 - 1) // q output divider .divq1().bits(2 - 1) // q output divider
}); });
rcc.cr.modify(|_, w| w.pll2on().set_bit()); rcc.cr.modify(|_, w| w.pll2on().on());
while rcc.cr.read().pll2rdy().bit_is_clear() {} while !rcc.cr.read().pll2rdy().is_ready() {}
// hclk 200 MHz, pclk 100 MHz // hclk 200 MHz, pclk 100 MHz
let dapb = 0b100; rcc.d1cfgr.write(|w|
rcc.d1cfgr.write(|w| unsafe { w.d1cpre().div1() // sys_ck not divided
w.d1cpre().bits(0) // sys_ck not divided .hpre().div2() // rcc_hclk3 = sys_d1cpre_ck / 2
.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2 .d1ppre().div2() // rcc_pclk3 = rcc_hclk3 / 2
.d1ppre().bits(dapb) // rcc_pclk3 = rcc_hclk3 / 2 );
}); rcc.d2cfgr.write(|w|
rcc.d2cfgr.write(|w| unsafe { w.d2ppre1().div2() // rcc_pclk1 = rcc_hclk3 / 2
w.d2ppre1().bits(dapb) // rcc_pclk1 = rcc_hclk3 / 2 .d2ppre2().div2() // rcc_pclk2 = rcc_hclk3 / 2
.d2ppre2().bits(dapb) // rcc_pclk2 = rcc_hclk3 / 2 );
rcc.d3cfgr.write(|w|
}); w.d3ppre().div2() // rcc_pclk4 = rcc_hclk3 / 2
rcc.d3cfgr.write(|w| unsafe { );
w.d3ppre().bits(dapb) // rcc_pclk4 = rcc_hclk3 / 2
});
// 2 wait states, 0b10 programming delay // 2 wait states, 0b10 programming delay
// 185-210 MHz // 185-210 MHz
@ -172,27 +172,22 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
while flash.acr.read().latency().bits() != 2 {} while flash.acr.read().latency().bits() != 2 {}
// CSI for I/O compensationc ell // CSI for I/O compensationc ell
rcc.cr.modify(|_, w| w.csion().set_bit()); rcc.cr.modify(|_, w| w.csion().on());
while rcc.cr.read().csirdy().bit_is_clear() {} while !rcc.cr.read().csirdy().is_ready() {}
// Set system clock to pll1_p // Set system clock to pll1_p
rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p rcc.cfgr.modify(|_, w| w.sw().pll1());
while rcc.cfgr.read().sws().bits() != 0b011 {} while !rcc.cfgr.read().sws().is_pll1() {}
rcc.d1ccipr.write(|w| unsafe { rcc.d1ccipr.write(|w| w.ckpersel().hse());
w.ckpersrc().bits(1) // hse_ck rcc.d2ccip1r.modify(|_, w|
}); w.spi123sel().pll2_p()
rcc.d2ccip1r.modify(|_, w| unsafe { .spi45sel().pll2_q()
w.spi123src().bits(1) // pll2_p );
.spi45src().bits(1) // pll2_q rcc.d3ccipr.modify(|_, w| w.spi6sel().pll2_q());
});
rcc.d3ccipr.modify(|_, w| unsafe {
w.spi6src().bits(1) // pll2_q
});
} }
fn io_compensation_setup(syscfg: &stm32::SYSCFG) { fn io_compensation_setup(syscfg: &pac::SYSCFG) {
syscfg.cccsr.modify(|_, w| syscfg.cccsr.modify(|_, w|
w.en().set_bit() w.en().set_bit()
.cs().clear_bit() .cs().clear_bit()
@ -201,27 +196,27 @@ fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
while syscfg.cccsr.read().ready().bit_is_clear() {} while syscfg.cccsr.read().ready().bit_is_clear() {}
} }
fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD,
gpioe: &stm32::GPIOE, gpiof: &stm32::GPIOF, gpiog: &stm32::GPIOG) { gpioe: &pac::GPIOE, gpiof: &pac::GPIOF, gpiog: &pac::GPIOG) {
// FP_LED0 // FP_LED0
gpiod.otyper.modify(|_, w| w.ot5().push_pull()); gpiod.otyper.modify(|_, w| w.ot5().push_pull());
gpiod.moder.modify(|_, w| w.moder5().output()); gpiod.moder.modify(|_, w| w.moder5().output());
gpiod.odr.modify(|_, w| w.odr5().clear_bit()); gpiod.odr.modify(|_, w| w.odr5().low());
// FP_LED1 // FP_LED1
gpiod.otyper.modify(|_, w| w.ot6().push_pull()); gpiod.otyper.modify(|_, w| w.ot6().push_pull());
gpiod.moder.modify(|_, w| w.moder6().output()); gpiod.moder.modify(|_, w| w.moder6().output());
gpiod.odr.modify(|_, w| w.odr6().clear_bit()); gpiod.odr.modify(|_, w| w.odr6().low());
// LED_FP2 // LED_FP2
gpiog.otyper.modify(|_, w| w.ot4().push_pull()); gpiog.otyper.modify(|_, w| w.ot4().push_pull());
gpiog.moder.modify(|_, w| w.moder4().output()); gpiog.moder.modify(|_, w| w.moder4().output());
gpiog.odr.modify(|_, w| w.odr4().clear_bit()); gpiog.odr.modify(|_, w| w.odr4().low());
// LED_FP3 // LED_FP3
gpiod.otyper.modify(|_, w| w.ot12().push_pull()); gpiod.otyper.modify(|_, w| w.ot12().push_pull());
gpiod.moder.modify(|_, w| w.moder12().output()); gpiod.moder.modify(|_, w| w.moder12().output());
gpiod.odr.modify(|_, w| w.odr12().clear_bit()); gpiod.odr.modify(|_, w| w.odr12().low());
// AFE0_A0,1: PG2,PG3 // AFE0_A0,1: PG2,PG3
gpiog.otyper.modify(|_, w| gpiog.otyper.modify(|_, w|
@ -233,8 +228,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
.moder3().output() .moder3().output()
); );
gpiog.odr.modify(|_, w| gpiog.odr.modify(|_, w|
w.odr2().clear_bit() w.odr2().low()
.odr3().clear_bit() .odr3().low()
); );
// ADC0 // ADC0
@ -274,12 +269,12 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
// DAC0_LDAC: PE11 // DAC0_LDAC: PE11
gpioe.moder.modify(|_, w| w.moder11().output()); gpioe.moder.modify(|_, w| w.moder11().output());
gpioe.otyper.modify(|_, w| w.ot11().push_pull()); gpioe.otyper.modify(|_, w| w.ot11().push_pull());
gpioe.odr.modify(|_, w| w.odr11().clear_bit()); gpioe.odr.modify(|_, w| w.odr11().low());
// DAC_CLR: PE12 // DAC_CLR: PE12
gpioe.moder.modify(|_, w| w.moder12().output()); gpioe.moder.modify(|_, w| w.moder12().output());
gpioe.otyper.modify(|_, w| w.ot12().push_pull()); gpioe.otyper.modify(|_, w| w.ot12().push_pull());
gpioe.odr.modify(|_, w| w.odr12().set_bit()); gpioe.odr.modify(|_, w| w.odr12().high());
// AFE1_A0,1: PD14,PD15 // AFE1_A0,1: PD14,PD15
gpiod.otyper.modify(|_, w| gpiod.otyper.modify(|_, w|
@ -291,8 +286,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
.moder15().output() .moder15().output()
); );
gpiod.odr.modify(|_, w| gpiod.odr.modify(|_, w|
w.odr14().clear_bit() w.odr14().low()
.odr15().clear_bit() .odr15().low()
); );
// ADC1 // ADC1
@ -332,127 +327,121 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
// DAC1_LDAC: PE15 // DAC1_LDAC: PE15
gpioe.moder.modify(|_, w| w.moder15().output()); gpioe.moder.modify(|_, w| w.moder15().output());
gpioe.otyper.modify(|_, w| w.ot15().push_pull()); gpioe.otyper.modify(|_, w| w.ot15().push_pull());
gpioe.odr.modify(|_, w| w.odr15().clear_bit()); gpioe.odr.modify(|_, w| w.odr15().low());
} }
// ADC0 // ADC0
fn spi1_setup(spi1: &stm32::SPI1) { fn spi1_setup(spi1: &pac::SPI1) {
spi1.cfg1.modify(|_, w| { spi1.cfg1.modify(|_, w|
w.mbr().bits(1) // clk/4 w.mbr().div4()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().one_frame() .fthlv().one_frame()
}); );
spi1.cfg2.modify(|_, w| unsafe { spi1.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().set_bit() .cpol().idle_high()
.cpha().set_bit() .cpha().second_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b10) // simplex receiver .comm().receiver()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(6) // master SS idle .mssi().bits(6)
}); );
spi1.cr2.modify(|_, w| { spi1.cr2.modify(|_, w| w.tsize().bits(1));
w.tsize().bits(1) spi1.cr1.write(|w| w.spe().enabled());
});
spi1.cr1.write(|w| w.spe().set_bit());
} }
// ADC1 // ADC1
fn spi5_setup(spi5: &stm32::SPI5) { fn spi5_setup(spi5: &pac::SPI5) {
spi5.cfg1.modify(|_, w| { spi5.cfg1.modify(|_, w|
w.mbr().bits(1) // clk/4 w.mbr().div4()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().one_frame() .fthlv().one_frame()
}); );
spi5.cfg2.modify(|_, w| unsafe { spi5.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().set_bit() .cpol().idle_high()
.cpha().set_bit() .cpha().second_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b10) // simplex receiver .comm().receiver()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(6) // master SS idle .mssi().bits(6)
}); );
spi5.cr2.modify(|_, w| { spi5.cr2.modify(|_, w| w.tsize().bits(1));
w.tsize().bits(1) spi5.cr1.write(|w| w.spe().enabled());
});
spi5.cr1.write(|w| w.spe().set_bit());
} }
// DAC0 // DAC0
fn spi2_setup(spi2: &stm32::SPI2) { fn spi2_setup(spi2: &pac::SPI2) {
spi2.cfg1.modify(|_, w| { spi2.cfg1.modify(|_, w|
w.mbr().bits(0) // clk/2 w.mbr().div2()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().one_frame() .fthlv().one_frame()
}); );
spi2.cfg2.modify(|_, w| unsafe { spi2.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().clear_bit() .cpol().idle_low()
.cpha().clear_bit() .cpha().first_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b01) // simplex transmitter .comm().transmitter()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(0) // master SS idle .mssi().bits(0)
}); );
spi2.cr2.modify(|_, w| w.tsize().bits(0)); spi2.cr2.modify(|_, w| w.tsize().bits(0));
spi2.cr1.write(|w| w.spe().enabled()); spi2.cr1.write(|w| w.spe().enabled());
spi2.cr1.modify(|_, w| w.cstart().started()); spi2.cr1.modify(|_, w| w.cstart().started());
} }
// DAC1 // DAC1
fn spi4_setup(spi4: &stm32::SPI4) { fn spi4_setup(spi4: &pac::SPI4) {
spi4.cfg1.modify(|_, w| { spi4.cfg1.modify(|_, w|
w.mbr().bits(0) // clk/2 w.mbr().div2()
.dsize().bits(16 - 1) .dsize().bits(16 - 1)
.fthvl().one_frame() .fthlv().one_frame()
}); );
spi4.cfg2.modify(|_, w| unsafe { spi4.cfg2.modify(|_, w|
w.afcntr().set_bit() w.afcntr().controlled()
.ssom().set_bit() // ss deassert between frames during midi .ssom().not_asserted()
.ssoe().set_bit() // ss output enable .ssoe().enabled()
.ssiop().clear_bit() // ss active low .ssiop().active_low()
.ssm().clear_bit() // PAD counts .ssm().disabled()
.cpol().clear_bit() .cpol().idle_low()
.cpha().clear_bit() .cpha().first_edge()
.lsbfrst().clear_bit() .lsbfrst().msbfirst()
.master().set_bit() .master().master()
.sp().bits(0) // motorola .sp().motorola()
.comm().bits(0b01) // simplex transmitter .comm().transmitter()
.ioswp().clear_bit() .ioswp().disabled()
.midi().bits(0) // master inter data idle .midi().bits(0)
.mssi().bits(0) // master SS idle .mssi().bits(0)
}); );
spi4.cr2.modify(|_, w| { spi4.cr2.modify(|_, w| w.tsize().bits(0));
w.tsize().bits(0)
});
spi4.cr1.write(|w| w.spe().enabled()); spi4.cr1.write(|w| w.spe().enabled());
spi4.cr1.modify(|_, w| w.cstart().started()); spi4.cr1.modify(|_, w| w.cstart().started());
} }
fn tim2_setup(tim2: &stm32::TIM2) { fn tim2_setup(tim2: &pac::TIM2) {
tim2.psc.write(|w| unsafe { w.psc().bits(200 - 1) }); // from 200 MHz tim2.psc.write(|w| w.psc().bits(200 - 1)); // from 200 MHz
tim2.arr.write(|w| unsafe { w.bits(2 - 1) }); // µs tim2.arr.write(|w| unsafe { w.bits(2 - 1) }); // µs
tim2.dier.write(|w| w.ude().set_bit()); tim2.dier.write(|w| w.ude().set_bit());
tim2.egr.write(|w| w.ug().set_bit()); tim2.egr.write(|w| w.ug().set_bit());
@ -461,15 +450,15 @@ fn tim2_setup(tim2: &stm32::TIM2) {
.cen().set_bit()); // enable .cen().set_bit()); // enable
} }
fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) {
dma1.s0cr.modify(|_, w| w.en().clear_bit()); dma1.st[0].cr.modify(|_, w| w.en().clear_bit());
while dma1.s0cr.read().en().bit_is_set() {} while dma1.st[0].cr.read().en().bit_is_set() {}
dma1.s0par.write(|w| unsafe { w.pa().bits(pa0 as u32) }); dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) });
dma1.s0m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) });
dma1.s0ndtr.write(|w| unsafe { w.ndt().bits(1) }); dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) });
dmamux1.ccr[0].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up());
dma1.s0cr.modify(|_, w| unsafe { dma1.st[0].cr.modify(|_, w| unsafe {
w.pl().bits(0b01) // medium w.pl().bits(0b01) // medium
.circ().set_bit() // reload ndtr .circ().set_bit() // reload ndtr
.msize().bits(0b10) // 32 .msize().bits(0b10) // 32
@ -482,17 +471,17 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
.dir().bits(0b01) // memory_to_peripheral .dir().bits(0b01) // memory_to_peripheral
.pfctrl().clear_bit() // dma is FC .pfctrl().clear_bit() // dma is FC
}); });
dma1.s0fcr.modify(|_, w| w.dmdis().clear_bit()); dma1.st[0].fcr.modify(|_, w| w.dmdis().clear_bit());
dma1.s0cr.modify(|_, w| w.en().set_bit()); dma1.st[0].cr.modify(|_, w| w.en().set_bit());
dma1.s1cr.modify(|_, w| w.en().clear_bit()); dma1.st[1].cr.modify(|_, w| w.en().clear_bit());
while dma1.s1cr.read().en().bit_is_set() {} while dma1.st[1].cr.read().en().bit_is_set() {}
dma1.s1par.write(|w| unsafe { w.pa().bits(pa1 as u32) }); dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) });
dma1.s1m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) });
dma1.s1ndtr.write(|w| unsafe { w.ndt().bits(1) }); dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) });
dmamux1.ccr[1].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up());
dma1.s1cr.modify(|_, w| unsafe { dma1.st[1].cr.modify(|_, w| unsafe {
w.pl().bits(0b01) // medium w.pl().bits(0b01) // medium
.circ().set_bit() // reload ndtr .circ().set_bit() // reload ndtr
.msize().bits(0b10) // 32 .msize().bits(0b10) // 32
@ -505,21 +494,16 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
.dir().bits(0b01) // memory_to_peripheral .dir().bits(0b01) // memory_to_peripheral
.pfctrl().clear_bit() // dma is FC .pfctrl().clear_bit() // dma is FC
}); });
dma1.s1fcr.modify(|_, w| w.dmdis().clear_bit()); dma1.st[1].fcr.modify(|_, w| w.dmdis().clear_bit());
dma1.s1cr.modify(|_, w| w.en().set_bit()); dma1.st[1].cr.modify(|_, w| w.en().set_bit());
} }
type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>; const SCALE: f32 = ((1 << 15) - 1) as f32;
static SPIP: Mutex<RefCell<SpiPs>> = Mutex::new(RefCell::new(None));
#[link_section = ".sram1.datspi"] #[link_section = ".sram1.datspi"]
static mut DAT: u32 = 0x201; // EN | CSTART static mut DAT: u32 = 0x201; // EN | CSTART
static TIME: AtomicU32 = AtomicU32::new(0); // static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
#[link_section = ".sram3.eth"]
static mut ETHERNET: eth::Device = eth::Device::new();
const TCP_RX_BUFFER_SIZE: usize = 8192; const TCP_RX_BUFFER_SIZE: usize = 8192;
const TCP_TX_BUFFER_SIZE: usize = 8192; const TCP_TX_BUFFER_SIZE: usize = 8192;
@ -535,11 +519,28 @@ macro_rules! create_socket {
) )
} }
#[rtfm::app(device = stm32h7::stm32h743)]
const APP: () = {
static SPI: (pac::SPI1, pac::SPI2, pac::SPI4, pac::SPI5) = ();
static ETHERNET_PERIPH: (pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL) = ();
#[entry] static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2];
fn main() -> ! { static mut IIR_CH: [IIR; 2] = [
let mut cp = CorePeripherals::take().unwrap(); IIR {
let dp = Peripherals::take().unwrap(); ba: [0., 0., 0., 0., 0.],
y_offset: 0.,
y_min: -SCALE - 1.,
y_max: SCALE
};
2];
#[link_section = ".sram3.eth"]
static mut ETHERNET: eth::Device = eth::Device::new();
#[init(schedule = [tick])]
fn init(c: init::Context) -> init::LateResources {
let dp = c.device;
let cp = c.core;
let rcc = dp.RCC; let rcc = dp.RCC;
rcc_reset(&rcc); rcc_reset(&rcc);
@ -554,17 +555,10 @@ fn main() -> ! {
rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
io_compensation_setup(&dp.SYSCFG); io_compensation_setup(&dp.SYSCFG);
// 100 MHz
cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core);
cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10);
cp.SYST.enable_counter();
cp.SYST.enable_interrupt();
unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority
cp.SCB.enable_icache(); cp.SCB.enable_icache();
// TODO: ETH DMA coherence issues // TODO: ETH DMA coherence issues
// cp.SCB.enable_dcache(&mut cp.CPUID); // cp.SCB.enable_dcache(&mut cp.CPUID);
cp.DWT.enable_cycle_counter(); // cp.DWT.enable_cycle_counter();
rcc.ahb4enr.modify(|_, w| rcc.ahb4enr.modify(|_, w|
w.gpioaen().set_bit() w.gpioaen().set_bit()
@ -615,21 +609,33 @@ fn main() -> ! {
rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
// work around the SPI stall erratum // work around the SPI stall erratum
//let dbgmcu = dp.DBGMCU; let dbgmcu = dp.DBGMCU;
//dbgmcu.apb1lfz1.modify(|_, w| w.stop_tim2().set_bit()); // stop tim2 in debug dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit());
unsafe { ptr::write_volatile(0x5c00_103c as *mut usize, 0x0000_0001) };
tim2_setup(&dp.TIM2);
eth::setup(&rcc, &dp.SYSCFG); eth::setup(&rcc, &dp.SYSCFG);
eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG);
let device = unsafe { &mut ETHERNET }; // c.schedule.tick(rtfm::Instant::now()).unwrap();
init::LateResources {
SPI: (spi1, spi2, spi4, spi5),
ETHERNET_PERIPH: (dp.ETHERNET_MAC, dp.ETHERNET_DMA, dp.ETHERNET_MTL),
}
}
#[idle(resources = [ETHERNET, ETHERNET_PERIPH, IIR_STATE, IIR_CH])]
fn idle(c: idle::Context) -> ! {
let (MAC, DMA, MTL) = c.resources.ETHERNET_PERIPH;
let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]);
unsafe { device.init(hardware_addr) }; unsafe { c.resources.ETHERNET.init(hardware_addr, MAC, DMA, MTL) };
let mut neighbor_cache_storage = [None; 8]; let mut neighbor_cache_storage = [None; 8];
let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]);
let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99);
let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)]; let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)];
let mut iface = net::iface::EthernetInterfaceBuilder::new(device) let mut iface = net::iface::EthernetInterfaceBuilder::new(c.resources.ETHERNET)
.ethernet_addr(hardware_addr) .ethernet_addr(hardware_addr)
.neighbor_cache(neighbor_cache) .neighbor_cache(neighbor_cache)
.ip_addrs(&mut ip_addrs[..]) .ip_addrs(&mut ip_addrs[..])
@ -639,38 +645,49 @@ fn main() -> ! {
create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0);
create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1);
unsafe { eth::enable_interrupt(); } // unsafe { eth::enable_interrupt(DMA); }
unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio let mut time = 0u32;
cp.NVIC.enable(stm32::Interrupt::ETH); let mut next_ms = rtfm::Instant::now();
next_ms += 200_000.cycles();
tim2_setup(&dp.TIM2);
unsafe { cp.NVIC.set_priority(stm32::Interrupt::SPI1, 0); } // highest prio
cortex_m::interrupt::free(|cs| {
cp.NVIC.enable(stm32::Interrupt::SPI1);
SPIP.borrow(cs).replace(Some((spi1, spi2, spi4, spi5)));
});
let mut last = 0;
let mut server = Server::new(); let mut server = Server::new();
let mut iir_state: resources::IIR_STATE = c.resources.IIR_STATE;
let mut iir_ch: resources::IIR_CH = c.resources.IIR_CH;
loop { loop {
// if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { }
let time = TIME.load(Ordering::Relaxed); let tick = rtfm::Instant::now() > next_ms;
if tick {
next_ms += 200_000.cycles();
time += 1;
}
{ {
let socket = &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle0); let socket = &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle0);
if !(socket.is_open() || socket.is_listening()) { if socket.state() == net::socket::TcpState::CloseWait {
socket.close();
} else if !(socket.is_open() || socket.is_listening()) {
socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
} else if last != time && socket.can_send() { } else if tick && socket.can_send() {
last = time; let s = iir_state.lock(|iir_state| Status {
handle_status(socket, time); t: time,
x0: iir_state[0][0],
y0: iir_state[0][2],
x1: iir_state[1][0],
y1: iir_state[1][2]
});
json_reply(socket, &s);
} }
} }
{ {
let socket = &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle1); let socket = &mut *sockets.get::<net::socket::TcpSocket>(tcp_handle1);
if !(socket.is_open() || socket.is_listening()) { if socket.state() == net::socket::TcpState::CloseWait {
socket.close();
} else if !(socket.is_open() || socket.is_listening()) {
socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
} else { } else {
server.handle_command(socket); server.poll(socket, |req: &Request| {
if req.channel < 2 {
iir_ch.lock(|iir_ch| iir_ch[req.channel as usize] = req.iir);
}
});
} }
} }
@ -679,10 +696,77 @@ fn main() -> ! {
Err(net::Error::Unrecognized) => true, Err(net::Error::Unrecognized) => true,
Err(e) => { info!("iface poll error: {:?}", e); true } Err(e) => { info!("iface poll error: {:?}", e); true }
} { } {
cortex_m::asm::wfi(); // cortex_m::asm::wfi();
} }
} }
} }
#[task(priority = 1, schedule = [tick])]
fn tick(c: tick::Context) {
static mut TIME: u32 = 0;
*TIME += 1;
const PERIOD: u32 = 200_000_000;
c.schedule.tick(c.scheduled + PERIOD.cycles()).unwrap();
}
// seems to slow it down
// #[link_section = ".data.spi1"]
#[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 2)]
fn SPI1(c: SPI1::Context) {
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
let (spi1, spi2, spi4, spi5) = c.resources.SPI;
let iir_ch = c.resources.IIR_CH;
let mut iir_state = c.resources.IIR_STATE;
let sr = spi1.sr.read();
if sr.eot().bit_is_set() {
spi1.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi1.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = iir_ch[0].update(&mut iir_state[0], x0);
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi2.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
let sr = spi5.sr.read();
if sr.eot().bit_is_set() {
spi5.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi5.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = iir_ch[1].update(&mut iir_state[1], x0);
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi4.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
}
/*
#[interrupt(resources = [ETHERNET_PERIPH], priority = 1)]
fn ETH(c: ETH::Context) {
let dma = &c.resources.ETHERNET_PERIPH.1;
ETHERNET_PENDING.store(true, Ordering::Relaxed);
unsafe { eth::interrupt_handler(dma) }
}
*/
extern "C" {
// hw interrupt handlers for RTFM to use for scheduling tasks
// one per priority
fn DCMI();
fn JPEG();
fn SDMMC();
}
};
#[derive(Deserialize,Serialize)] #[derive(Deserialize,Serialize)]
struct Request { struct Request {
@ -696,7 +780,16 @@ struct Response<'a> {
message: &'a str, message: &'a str,
} }
fn reply<T: Serialize>(socket: &mut net::socket::TcpSocket, msg: &T) { #[derive(Serialize)]
struct Status {
t: u32,
x0: f32,
y0: f32,
x1: f32,
y1: f32
}
fn json_reply<T: Serialize>(socket: &mut net::socket::TcpSocket, msg: &T) {
let mut u: String<U128> = to_string(msg).unwrap(); let mut u: String<U128> = to_string(msg).unwrap();
u.push('\n').unwrap(); u.push('\n').unwrap();
socket.write_str(&u).unwrap(); socket.write_str(&u).unwrap();
@ -712,7 +805,11 @@ impl Server {
Self { data: Vec::new(), discard: false } Self { data: Vec::new(), discard: false }
} }
fn handle_command(&mut self, socket: &mut net::socket::TcpSocket) { fn poll<T, F, R>(&mut self, socket: &mut net::socket::TcpSocket, f: F) -> Option<R>
where
T: DeserializeOwned,
F: FnOnce(&T) -> R,
{
while socket.can_recv() { while socket.can_recv() {
let found = socket.recv(|buf| { let found = socket.recv(|buf| {
let (len, found) = match buf.iter().position(|&c| c as char == '\n') { let (len, found) = match buf.iter().position(|&c| c as char == '\n') {
@ -727,114 +824,30 @@ impl Server {
} }
(len, found) (len, found)
}).unwrap(); }).unwrap();
if !found { if found {
continue; if self.discard {
}
let resp = if self.discard {
self.discard = false; self.discard = false;
Response{ code: 520, message: "command buffer overflow" } json_reply(socket, &Response { code: 520, message: "command buffer overflow" });
self.data.clear();
} else { } else {
match from_slice::<Request>(&self.data) { let r = from_slice::<T>(&self.data);
Ok(request) => { self.data.clear();
if request.channel > 1 { match r {
Response{ code: 530, message: "invalid channel" } Ok(res) => {
} else { let r = f(&res);
cortex_m::interrupt::free(|_| { json_reply(socket, &Response { code: 200, message: "ok" });
unsafe { IIR_CH[request.channel as usize] = request.iir; }; return Some(r);
});
Response{ code: 200, message: "ok" }
}
}, },
Err(err) => { Err(err) => {
warn!("parse error {:?}", err); warn!("parse error {:?}", err);
Response{ code: 550, message: "parse error" } json_reply(socket, &Response { code: 550, message: "parse error" });
}, },
} }
};
self.data.clear();
reply(socket, &resp);
socket.close();
} }
} }
}
fn handle_status(socket: &mut net::socket::TcpSocket, time: u32) {
let s = unsafe { Status{
t: time,
x0: IIR_STATE[0][0],
y0: IIR_STATE[0][2],
x1: IIR_STATE[1][0],
y1: IIR_STATE[1][2],
}};
reply(socket, &s);
}
#[derive(Serialize)]
struct Status {
t: u32,
x0: f32,
y0: f32,
x1: f32,
y1: f32
}
const SCALE: f32 = ((1 << 15) - 1) as f32;
static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2];
static mut IIR_CH: [IIR; 2] = [
IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0.,
y_min: -SCALE - 1., y_max: SCALE }; 2];
// seems to slow it down
// #[link_section = ".data.spi1"]
#[interrupt]
fn SPI1() {
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
cortex_m::interrupt::free(|cs| {
let spip = SPIP.borrow(cs).borrow();
let (spi1, spi2, spi4, spi5) = spip.as_ref().unwrap();
let sr = spi1.sr.read();
if sr.eot().bit_is_set() {
spi1.ifcr.write(|w| w.eotc().set_bit());
} }
if sr.rxp().bit_is_set() { None
let rxdr = &spi1.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) };
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi2.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
} }
let sr = spi5.sr.read();
if sr.eot().bit_is_set() {
spi5.ifcr.write(|w| w.eotc().set_bit());
}
if sr.rxp().bit_is_set() {
let rxdr = &spi5.rxdr as *const _ as *const u16;
let a = unsafe { ptr::read_volatile(rxdr) };
let x0 = f32::from(a as i16);
let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) };
let d = y0 as i16 as u16 ^ 0x8000;
let txdr = &spi4.txdr as *const _ as *mut u16;
unsafe { ptr::write_volatile(txdr, d) };
}
});
#[cfg(feature = "bkpt")]
cortex_m::asm::bkpt();
}
#[interrupt]
fn ETH() {
ETHERNET_PENDING.store(true, Ordering::Relaxed);
unsafe { eth::interrupt_handler() }
}
#[exception]
fn SysTick() {
TIME.fetch_add(1, Ordering::Relaxed);
} }
#[exception] #[exception]