diff --git a/Cargo.lock b/Cargo.lock index e6709d2..b6c54e9 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1,5 +1,10 @@ # This file is automatically @generated by Cargo. # It is not intended for manual editing. +[[package]] +name = "aligned" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" + [[package]] name = "aligned" version = "0.3.1" @@ -13,7 +18,7 @@ name = "as-slice" version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "generic-array 0.12.0 (registry+https://github.com/rust-lang/crates.io-index)", + "generic-array 0.12.3 (registry+https://github.com/rust-lang/crates.io-index)", "stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -27,19 +32,30 @@ dependencies = [ [[package]] name = "bitflags" -version = "1.0.4" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "byteorder" -version = "1.3.1" +version = "1.3.2" source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "cfg-if" -version = "0.1.7" +version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" +[[package]] +name = "cortex-m" +version = "0.5.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "aligned 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", + "bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", + "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "cortex-m" version = "0.6.0" @@ -57,12 +73,12 @@ source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-semihosting 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)", - "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", + "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "cortex-m-rt" -version = "0.6.8" +version = "0.6.10" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "cortex-m-rt-macros 0.1.5 (registry+https://github.com/rust-lang/crates.io-index)", @@ -74,10 +90,31 @@ name = "cortex-m-rt-macros" version = "0.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "proc-macro2 0.4.28 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", + "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", "rand 0.5.6 (registry+https://github.com/rust-lang/crates.io-index)", - "syn 0.15.33 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.42 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "cortex-m-rtfm" +version = "0.5.0-alpha.1" +source = "git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" +dependencies = [ + "cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rt 0.6.10 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", + "heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "cortex-m-rtfm-macros" +version = "0.5.0-alpha.1" +source = "git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" +dependencies = [ + "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.42 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -90,7 +127,7 @@ dependencies = [ [[package]] name = "generic-array" -version = "0.11.1" +version = "0.12.3" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -98,7 +135,7 @@ dependencies = [ [[package]] name = "generic-array" -version = "0.12.0" +version = "0.13.2" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -109,25 +146,25 @@ name = "hash32" version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)", + "byteorder 1.3.2 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "heapless" -version = "0.4.4" +version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", - "generic-array 0.11.1 (registry+https://github.com/rust-lang/crates.io-index)", + "generic-array 0.13.2 (registry+https://github.com/rust-lang/crates.io-index)", "hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "log" -version = "0.4.6" +version = "0.4.8" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "cfg-if 0.1.7 (registry+https://github.com/rust-lang/crates.io-index)", + "cfg-if 0.1.9 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -135,11 +172,6 @@ name = "managed" version = "0.7.1" source = "registry+https://github.com/rust-lang/crates.io-index" -[[package]] -name = "panic-abort" -version = "0.3.1" -source = "registry+https://github.com/rust-lang/crates.io-index" - [[package]] name = "panic-semihosting" version = "0.5.2" @@ -151,7 +183,7 @@ dependencies = [ [[package]] name = "proc-macro2" -version = "0.4.28" +version = "0.4.30" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "unicode-xid 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -159,10 +191,10 @@ dependencies = [ [[package]] name = "quote" -version = "0.6.12" +version = "0.6.13" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "proc-macro2 0.4.28 (registry+https://github.com/rust-lang/crates.io-index)", + "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -214,29 +246,29 @@ source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "serde" -version = "1.0.91" +version = "1.0.98" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "serde_derive 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)", + "serde_derive 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "serde-json-core" version = "0.0.1" -source = "git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9#82fdca9eb08183f00480eea289e809e5dd37e9fe" +source = "git+https://github.com/quartiq/serde-json-core.git?rev=fc764de#fc764deb8dfb82e5cfcc6c5059d8d5c3031e0591" dependencies = [ - "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", - "serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)", + "heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", + "serde 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "serde_derive" -version = "1.0.91" +version = "1.0.98" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "proc-macro2 0.4.28 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", - "syn 0.15.33 (registry+https://github.com/rust-lang/crates.io-index)", + "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.42 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -244,8 +276,8 @@ name = "smoltcp" version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)", - "byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)", + "bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)", + "byteorder 1.3.2 (registry+https://github.com/rust-lang/crates.io-index)", "managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -255,15 +287,15 @@ version = "0.2.0" dependencies = [ "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", - "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", - "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", - "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", - "panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rt 0.6.10 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", + "heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", + "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)", "panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)", - "serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)", - "serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)", + "serde 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)", + "serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)", "smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", - "stm32h7 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)", + "stm32h7 0.8.0 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -273,22 +305,22 @@ source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "stm32h7" -version = "0.7.0" +version = "0.8.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", - "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rt 0.6.10 (registry+https://github.com/rust-lang/crates.io-index)", "vcell 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "syn" -version = "0.15.33" +version = "0.15.42" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "proc-macro2 0.4.28 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", + "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", "unicode-xid 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -316,27 +348,30 @@ dependencies = [ ] [metadata] +"checksum aligned 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "d39da9b88ae1a81c03c9c082b8db83f1d0e93914126041962af61034ab44c4a5" "checksum aligned 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "d3a316c7ea8e1e9ece54862c992def5a7ac14de9f5832b69d71760680efeeefa" "checksum as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "293dac66b274fab06f95e7efb05ec439a6b70136081ea522d270bc351ae5bb27" "checksum bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)" = "a3caf393d93b2d453e80638d0674597020cef3382ada454faacd43d1a55a735a" -"checksum bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)" = "228047a76f468627ca71776ecdebd732a3423081fcf5125585bcd7c49886ce12" -"checksum byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "a019b10a2a7cdeb292db131fc8113e57ea2a908f6e7894b0c3c671893b65dbeb" -"checksum cfg-if 0.1.7 (registry+https://github.com/rust-lang/crates.io-index)" = "11d43355396e872eefb45ce6342e4374ed7bc2b3a502d1b28e36d6e23c05d1f4" +"checksum bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3d155346769a6855b86399e9bc3814ab343cd3d62c7e985113d46a0ec3c281fd" +"checksum byteorder 1.3.2 (registry+https://github.com/rust-lang/crates.io-index)" = "a7c3dd8985a7111efc5c80b44e23ecdd8c007de8ade3b96595387e812b957cf5" +"checksum cfg-if 0.1.9 (registry+https://github.com/rust-lang/crates.io-index)" = "b486ce3ccf7ffd79fdeb678eac06a9e6c09fc88d33836340becb8fffe87c5e33" +"checksum cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)" = "3c0b159a1e8306949579de3698c841dba58058197b65c60807194e4fa1e7a554" "checksum cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)" = "f3c18719fdc57db65668bfc977db9a0fa1a41d718c5d9cd4f652c9d4b0e0956a" "checksum cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "584a62cf37ddd834b8bfc21317bf3396915844298bf346dd1f4ca0572180ac7f" -"checksum cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)" = "7e1ccc9052352415ec4e3f762f4541098d012016f9354a1a5b2dede39b67f426" +"checksum cortex-m-rt 0.6.10 (registry+https://github.com/rust-lang/crates.io-index)" = "17805910e3ecf029bdbfcc42b7384d9e3d9e5626153fa810002c1ef9839338ac" "checksum cortex-m-rt-macros 0.1.5 (registry+https://github.com/rust-lang/crates.io-index)" = "d7ae692573e0acccb1579fef1abf5a5bf1d2f3f0149a22b16870ec9309aee25f" +"checksum cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "" +"checksum cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "" "checksum cortex-m-semihosting 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)" = "165f3f86f4d1031351a6c9dc8d5a3f8fae2050f9dd6ef925e3d675c232cc0e46" -"checksum generic-array 0.11.1 (registry+https://github.com/rust-lang/crates.io-index)" = "8107dafa78c80c848b71b60133954b4a58609a3a1a5f9af037ecc7f67280f369" -"checksum generic-array 0.12.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3c0f28c2f5bfb5960175af447a2da7c18900693738343dc896ffbcabd9839592" +"checksum generic-array 0.12.3 (registry+https://github.com/rust-lang/crates.io-index)" = "c68f0274ae0e023facc3c97b2e00f076be70e254bc851d972503b328db79b2ec" +"checksum generic-array 0.13.2 (registry+https://github.com/rust-lang/crates.io-index)" = "0ed1e761351b56f54eb9dcd0cfaca9fd0daecf93918e1cfc01c8a3d26ee7adcd" "checksum hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "12d790435639c06a7b798af9e1e331ae245b7ef915b92f70a39b4cf8c00686af" -"checksum heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)" = "e1ae80bbc62401ae8096976857172507cadbd2200f36670e5144634360a05959" -"checksum log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c84ec4b527950aa83a329754b01dbe3f58361d1c5efacd1f6d68c494d08a17c6" +"checksum heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c6c7ce2e47016f34d17acbf2fe5f9e0337ea59d2ab8ceecd9405b2336ffaca9b" +"checksum log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)" = "14b6052be84e6b71ab17edffc2eeabf5c2c3ae1fdb464aae35ac50c67a44e1f7" "checksum managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6" -"checksum panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "2c14a66511ed17b6a8b4256b868d7fd207836d891db15eea5195dbcaf87e630f" "checksum panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)" = "97cfb37c1d3b5f0cc18bf14485018cccd13bdd24f7b5bfd456c1d8760afef824" -"checksum proc-macro2 0.4.28 (registry+https://github.com/rust-lang/crates.io-index)" = "ba92c84f814b3f9a44c5cfca7d2ad77fa10710867d2bbb1b3d175ab5f47daa12" -"checksum quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)" = "faf4799c5d274f3868a4aae320a0a182cbd2baee377b378f080e16a23e9d80db" +"checksum proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)" = "cf3d2011ab5c909338f7887f4fc896d35932e29146c12c8d01da6b22a80ba759" +"checksum quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)" = "6ce23b6b870e8f94f81fb0a363d65d86675884b34a09043c81e5562f11c1f8e1" "checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f" "checksum rand 0.5.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c618c47cd3ebd209790115ab837de41425723956ad3ce2e6a7f09890947cacb9" "checksum rand_core 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "7a6fdeb83b075e8266dcc8762c22776f6877a63111121f5f8c7411e5be7eed4b" @@ -344,13 +379,13 @@ dependencies = [ "checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a" "checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403" "checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" -"checksum serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "a72e9b96fa45ce22a4bc23da3858dfccfd60acd28a25bcd328a98fdd6bea43fd" -"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)" = "" -"checksum serde_derive 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "101b495b109a3e3ca8c4cbe44cf62391527cdfb6ba15821c5ce80bcd5ea23f9f" +"checksum serde 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "7fe5626ac617da2f2d9c48af5515a21d5a480dbd151e01bb1c355e26a3e68113" +"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)" = "" +"checksum serde_derive 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "01e69e1b8a631f245467ee275b8c757b818653c6d704cdbcaeb56b56767b529c" "checksum smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fef582369edb298c6c41319a544ca9c4e83622f226055ccfcb35974fbb55ed34" "checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" -"checksum stm32h7 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "64173a3f8edb1bf9e17b14861695da2a7e6ca98afc99e0f249b62e4962cc478d" -"checksum syn 0.15.33 (registry+https://github.com/rust-lang/crates.io-index)" = "ec52cd796e5f01d0067225a5392e70084acc4c0013fa71d55166d38a8b307836" +"checksum stm32h7 0.8.0 (registry+https://github.com/rust-lang/crates.io-index)" = "63001af508d3332bd2dd81d4212b69e10f45e8f5435b7dab5def36178b9c1c17" +"checksum syn 0.15.42 (registry+https://github.com/rust-lang/crates.io-index)" = "eadc09306ca51a40555dd6fc2b415538e9e18bc9f870e47b1a524a79fe2dcf5e" "checksum typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "612d636f949607bdf9b123b4a6f6d966dedf3ff669f7f045890d3a4a73948169" "checksum unicode-xid 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fc72304796d0818e357ead4e000d19c9c174ab23dc11093ac919054d20a6a7fc" "checksum vcell 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "45c297f0afb6928cd08ab1ff9d95e99392595ea25ae1b5ecf822ff8764e57a0d" diff --git a/Cargo.toml b/Cargo.toml index 7c900fb..0e87142 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -30,25 +30,32 @@ default-target = "thumbv7em-none-eabihf" cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] } cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-log = { version = "0.5", features = ["log-integration"] } -stm32h7 = { version = "0.7", features = ["stm32h7x3", "rt"] } log = "0.4" -panic-abort = "0.3" -panic-semihosting = { version = "0.5.2", optional = true } +panic-semihosting = { version = "0.5", optional = true } serde = { version = "1.0", features = ["derive"], default-features = false } -heapless = { version = "0.4" } +heapless = { version = "0.5" } [dependencies.serde-json-core] # version = "0.0" git = "https://github.com/quartiq/serde-json-core.git" -rev = "82fdca9" +rev = "fc764de" + +[dependencies.stm32h7] +version = "0.8" +features = ["stm32h743", "rt"] [dependencies.smoltcp] #git = "https://github.com/m-labs/smoltcp.git" -#rev = "cd893e6" +#rev = "0f61443" version = "0.5" features = ["proto-ipv4", "socket-tcp"] default-features = false +[dependencies.cortex-m-rtfm] +git = "https://github.com/japaric/cortex-m-rtfm" +rev = "fafeeb2" +features = ["timer-queue"] + [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] bkpt = [ ] diff --git a/src/eth.rs b/src/eth.rs index 7761817..211fa16 100644 --- a/src/eth.rs +++ b/src/eth.rs @@ -1,6 +1,5 @@ use core::{slice, cmp}; -use cortex_m; -use stm32h7::stm32h7x3 as stm32; +use stm32h7::stm32h743 as pac; use smoltcp::Result; use smoltcp::time::Instant; use smoltcp::wire::EthernetAddress; @@ -87,7 +86,7 @@ use self::cr_consts::*; const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102; -pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) { +pub fn setup(rcc: &pac::RCC, syscfg: &pac::SYSCFG) { rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); rcc.ahb1enr.modify(|_, w| { w.eth1macen().set_bit() @@ -99,8 +98,8 @@ pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) { //rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit()); } -pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, - gpioc: &stm32::GPIOC, gpiog: &stm32::GPIOG) { +pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, + gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) { // PA1 RMII_REF_CLK gpioa.moder.modify(|_, w| w.moder1().alternate()); gpioa.afrl.modify(|_, w| w.afr1().af11()); @@ -141,48 +140,40 @@ pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, const PHY_ADDR: u8 = 0; -fn phy_read(reg_addr: u8) -> u16 { - cortex_m::interrupt::free(|_cs| { - let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() }; - - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdioar.modify(|_, w| unsafe { - w - .pa().bits(PHY_ADDR) - .rda().bits(reg_addr) - .goc().bits(0b11) // read - .cr().bits(CLOCK_RANGE) - .mb().set_bit() - }); - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdiodr.read().md().bits() - }) +fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 { + while mac.macmdioar.read().mb().bit_is_set() {} + mac.macmdioar.modify(|_, w| unsafe { + w + .pa().bits(PHY_ADDR) + .rda().bits(reg_addr) + .goc().bits(0b11) // read + .cr().bits(CLOCK_RANGE) + .mb().set_bit() + }); + while mac.macmdioar.read().mb().bit_is_set() {} + mac.macmdiodr.read().md().bits() } -fn phy_write(reg_addr: u8, reg_data: u16) { - cortex_m::interrupt::free(|_cs| { - let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() }; - - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); - mac.macmdioar.modify(|_, w| unsafe { - w - .pa().bits(PHY_ADDR) - .rda().bits(reg_addr) - .goc().bits(0b01) // write - .cr().bits(CLOCK_RANGE) - .mb().set_bit() - }); - while mac.macmdioar.read().mb().bit_is_set() {} - }) +fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) { + while mac.macmdioar.read().mb().bit_is_set() {} + mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); + mac.macmdioar.modify(|_, w| unsafe { + w + .pa().bits(PHY_ADDR) + .rda().bits(reg_addr) + .goc().bits(0b01) // write + .cr().bits(CLOCK_RANGE) + .mb().set_bit() + }); + while mac.macmdioar.read().mb().bit_is_set() {} } // Writes a value to an extended PHY register in MMD address space -fn phy_write_ext(reg_addr: u16, reg_data: u16) { - phy_write(PHY_REG_CTL, 0x0003); // set address - phy_write(PHY_REG_ADDAR, reg_addr); - phy_write(PHY_REG_CTL, 0x4003); // set data - phy_write(PHY_REG_ADDAR, reg_data); +fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) { + phy_write(PHY_REG_CTL, 0x0003, mac); // set address + phy_write(PHY_REG_ADDAR, reg_addr, mac); + phy_write(PHY_REG_CTL, 0x4003, mac); // set data + phy_write(PHY_REG_ADDAR, reg_data, mac); } #[repr(align(4))] @@ -201,7 +192,7 @@ impl RxRing { } } - fn init(&mut self) { + unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) { assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0); @@ -214,17 +205,10 @@ impl RxRing { } } - cortex_m::interrupt::free(|_cs| unsafe { - let dma = &*stm32::ETHERNET_DMA::ptr(); - - dma.dmacrx_dlar.write(|w| { - w.bits(&self.desc_buf as *const _ as u32) - }); - - dma.dmacrx_rlr.write(|w| { - w.rdrl().bits(self.desc_buf.len() as u16 - 1) - }); - }); + let addr = &self.desc_buf as *const _ as u32; + assert_eq!(addr & 0x3, 0); + dma.dmacrx_dlar.write(|w| w.bits(addr)); + dma.dmacrx_rlr.write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1)); self.cur_desc = 0; for _ in 0..self.desc_buf.len() { @@ -259,11 +243,10 @@ impl RxRing { self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP; self.desc_buf[self.cur_desc][3] = EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN; - let addr = &self.desc_buf[self.cur_desc] as *const _; - cortex_m::interrupt::free(|_cs| { - let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() }; - dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr as u32) }); - }); + let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; + assert_eq!(addr & 0x3, 0); + let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA }; + dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) }); self.cur_desc = self.next_desc(); } @@ -285,7 +268,7 @@ impl TxRing { } } - fn init(&mut self) { + unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) { assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0); @@ -299,21 +282,13 @@ impl TxRing { } self.cur_desc = 0; - cortex_m::interrupt::free(|_cs| unsafe { - let dma = &*stm32::ETHERNET_DMA::ptr(); - - dma.dmactx_dlar.write(|w| { - w.bits(&self.desc_buf as *const _ as u32) - }); - - dma.dmactx_rlr.write(|w| { - w.tdrl().bits(self.desc_buf.len() as u16 - 1) - }); - - dma.dmactx_dtpr.write(|w| { - w.bits(&self.desc_buf[0] as *const _ as u32) - }); - }); + let addr = &self.desc_buf as *const _ as u32; + assert_eq!(addr & 0x3, 0); + dma.dmactx_dlar.write(|w| w.bits(addr)); + dma.dmactx_rlr.write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1)); + let addr = &self.desc_buf[0] as *const _ as u32; + assert_eq!(addr & 0x3, 0); + dma.dmactx_dtpr.write(|w| w.bits(addr)); } fn next_desc(&self) -> usize { @@ -337,11 +312,10 @@ impl TxRing { self.desc_buf[self.cur_desc][3] = EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD; self.cur_desc = self.next_desc(); - let addr = &self.desc_buf[self.cur_desc] as *const _; - cortex_m::interrupt::free(|_cs| { - let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() }; - dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr as u32) }); - }); + let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; + assert_eq!(addr & 0x3, 0); + let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA }; + dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) }); } } @@ -356,180 +330,174 @@ impl Device { } // After `init` is called, `Device` shall not be moved. - pub unsafe fn init(&mut self, mac: EthernetAddress) { - cortex_m::interrupt::free(|_cs| { - let eth_mac = &*stm32::ETHERNET_MAC::ptr(); - let eth_dma = &*stm32::ETHERNET_DMA::ptr(); - let _eth_mmc = &*stm32::ETHERNET_MMC::ptr(); - let eth_mtl = &*stm32::ETHERNET_MTL::ptr(); + pub unsafe fn init(&mut self, mac: EthernetAddress, + eth_mac: &pac::ETHERNET_MAC, + eth_dma: &pac::ETHERNET_DMA, + eth_mtl: &pac::ETHERNET_MTL, + ) { + eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); + while eth_dma.dmamr.read().swr().bit_is_set() {} - eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); - while eth_dma.dmamr.read().swr().bit_is_set() {} + // 200 MHz + eth_mac.mac1ustcr.modify(|_, w| w.tic_1us_cntr().bits(200 - 1)); - // 200 MHz - eth_mac.mac1ustcr.modify(|_, w| w.tic_1us_cntr().bits(200 - 1)); - - // Configuration Register - eth_mac.maccr.modify(|_, w| { - w - .arpen().clear_bit() - .ipc().set_bit() - .ipg().bits(0b000) // 96 bit - .ecrsfd().clear_bit() - .dcrs().clear_bit() - .bl().bits(0b00) // 19 - .prelen().bits(0b00) // 7 - // CRC stripping for Type frames - .cst().set_bit() - // Fast Ethernet speed - .fes().set_bit() - // Duplex mode - .dm().set_bit() - // Automatic pad/CRC stripping - .acs().set_bit() - // Retry disable in half-duplex mode - .dr().set_bit() - }); - eth_mac.macecr.modify(|_, w| { - w - .eipgen().clear_bit() - .usp().clear_bit() - .spen().clear_bit() - .dcrcc().clear_bit() - }); - // Set the MAC address - eth_mac.maca0lr.write(|w| - w.addrlo().bits( u32::from(mac.0[0]) | - (u32::from(mac.0[1]) << 8) | - (u32::from(mac.0[2]) << 16) | - (u32::from(mac.0[3]) << 24)) - ); - eth_mac.maca0hr.write(|w| - w.addrhi().bits( u16::from(mac.0[4]) | - (u16::from(mac.0[5]) << 8)) - .ae().set_bit() - //.sa().clear_bit() - //.mbc().bits(0b000000) - ); - // frame filter register - eth_mac.macpfr.modify(|_, w| { - w - .dntu().clear_bit() - .ipfe().clear_bit() - .vtfe().clear_bit() - .hpf().clear_bit() - .saf().clear_bit() - .saif().clear_bit() - .pcf().bits(0b00) - .dbf().clear_bit() - .pm().clear_bit() - .daif().clear_bit() - .hmc().clear_bit() - .huc().clear_bit() - // Receive All - .ra().clear_bit() - // Promiscuous mode - .pr().clear_bit() - }); - eth_mac.macwtr.write(|w| w.pwe().clear_bit()); - // Flow Control Register - eth_mac.macqtxfcr.modify(|_, w| { - // Pause time - w.pt().bits(0x100) - }); - eth_mac.macrxfcr.modify(|_, w| w); - eth_mtl.mtlrxqomr.modify(|_, w| - w - // Receive store and forward - .rsf().set_bit() - // Dropping of TCP/IP checksum error frames disable - .dis_tcp_ef().clear_bit() - // Forward error frames - .fep().clear_bit() - // Forward undersized good packets - .fup().clear_bit() - ); - eth_mtl.mtltxqomr.modify(|_, w| { - w - // Transmit store and forward - .tsf().set_bit() - }); - - if (phy_read(PHY_REG_ID1) != 0x0007) | (phy_read(PHY_REG_ID2) != 0xC131) { - error!("PHY ID error!"); - } - - phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET); - while phy_read(PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}; - phy_write_ext(PHY_REG_WUCSR, 0); - phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M); - /* - while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {}; - while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {}; - while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED) - != PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {}; - */ - - // operation mode register - eth_dma.dmamr.modify(|_, w| { - w - .intm().clear_bit() // FIXME: bits(0b00) - // Rx Tx priority ratio 1:1 - .pr().bits(0b000) - .txpr().clear_bit() - .da().clear_bit() - }); - // bus mode register - eth_dma.dmasbmr.modify(|_, w| { - // Address-aligned beats - w.aal().set_bit() - // Fixed burst - .fb().set_bit() - }); - eth_dma.dmaccr.modify(|_, w| { - w - .dsl().bits(0) - .pblx8().clear_bit() - .mss().bits(536) - }); - eth_dma.dmactx_cr.modify(|_, w| { - w - // Tx DMA PBL - .txpbl().bits(32) - .tse().clear_bit() - // Operate on second frame - .osf().clear_bit() - }); - - eth_dma.dmacrx_cr.modify(|_, w| { - w - // receive buffer size - .rbsz().bits(ETH_BUFFER_SIZE as u16) - // Rx DMA PBL - .rxpbl().bits(32) - // Disable flushing of received frames - .rpf().clear_bit() - }); - - self.rx.init(); - self.tx.init(); - - // Manage MAC transmission and reception - eth_mac.maccr.modify(|_, w| { - w.re().bit(true) // Receiver Enable - .te().bit(true) // Transmiter Enable - }); - eth_mtl.mtltxqomr.modify(|_, w| w.ftq().set_bit()); - - // Manage DMA transmission and reception - eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); - eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit()); - - eth_dma.dmacsr.modify(|_, w| - w.tps().set_bit() - .rps().set_bit() - ); + // Configuration Register + eth_mac.maccr.modify(|_, w| { + w + .arpen().clear_bit() + .ipc().set_bit() + .ipg().bits(0b000) // 96 bit + .ecrsfd().clear_bit() + .dcrs().clear_bit() + .bl().bits(0b00) // 19 + .prelen().bits(0b00) // 7 + // CRC stripping for Type frames + .cst().set_bit() + // Fast Ethernet speed + .fes().set_bit() + // Duplex mode + .dm().set_bit() + // Automatic pad/CRC stripping + .acs().set_bit() + // Retry disable in half-duplex mode + .dr().set_bit() }); + eth_mac.macecr.modify(|_, w| { + w + .eipgen().clear_bit() + .usp().clear_bit() + .spen().clear_bit() + .dcrcc().clear_bit() + }); + // Set the MAC address + eth_mac.maca0lr.write(|w| + w.addrlo().bits( u32::from(mac.0[0]) | + (u32::from(mac.0[1]) << 8) | + (u32::from(mac.0[2]) << 16) | + (u32::from(mac.0[3]) << 24)) + ); + eth_mac.maca0hr.write(|w| + w.addrhi().bits( u16::from(mac.0[4]) | + (u16::from(mac.0[5]) << 8)) + ); + // frame filter register + eth_mac.macpfr.modify(|_, w| { + w + .dntu().clear_bit() + .ipfe().clear_bit() + .vtfe().clear_bit() + .hpf().clear_bit() + .saf().clear_bit() + .saif().clear_bit() + .pcf().bits(0b00) + .dbf().clear_bit() + .pm().clear_bit() + .daif().clear_bit() + .hmc().clear_bit() + .huc().clear_bit() + // Receive All + .ra().clear_bit() + // Promiscuous mode + .pr().clear_bit() + }); + eth_mac.macwtr.write(|w| w.pwe().clear_bit()); + // Flow Control Register + eth_mac.macqtx_fcr.modify(|_, w| { + // Pause time + w.pt().bits(0x100) + }); + eth_mac.macrx_fcr.modify(|_, w| w); + eth_mtl.mtlrx_qomr.modify(|_, w| + w + // Receive store and forward + .rsf().set_bit() + // Dropping of TCP/IP checksum error frames disable + .dis_tcp_ef().clear_bit() + // Forward error frames + .fep().clear_bit() + // Forward undersized good packets + .fup().clear_bit() + ); + eth_mtl.mtltx_qomr.modify(|_, w| { + w + // Transmit store and forward + .tsf().set_bit() + }); + + if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007) | (phy_read(PHY_REG_ID2, eth_mac) != 0xC131) { + error!("PHY ID error!"); + } + + phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac); + while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}; + phy_write_ext(PHY_REG_WUCSR, 0, eth_mac); + phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M, eth_mac); + /* + while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {}; + while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {}; + while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED) + != PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {}; + */ + + // operation mode register + eth_dma.dmamr.modify(|_, w| { + w + .intm().bits(0b00) + // Rx Tx priority ratio 1:1 + .pr().bits(0b000) + .txpr().clear_bit() + .da().clear_bit() + }); + // bus mode register + eth_dma.dmasbmr.modify(|_, w| { + // Address-aligned beats + w.aal().set_bit() + // Fixed burst + .fb().set_bit() + }); + eth_dma.dmaccr.modify(|_, w| { + w + .dsl().bits(0) + .pblx8().clear_bit() + .mss().bits(536) + }); + eth_dma.dmactx_cr.modify(|_, w| { + w + // Tx DMA PBL + .txpbl().bits(32) + .tse().clear_bit() + // Operate on second frame + .osf().clear_bit() + }); + + eth_dma.dmacrx_cr.modify(|_, w| { + w + // receive buffer size + .rbsz().bits(ETH_BUFFER_SIZE as u16) + // Rx DMA PBL + .rxpbl().bits(32) + // Disable flushing of received frames + .rpf().clear_bit() + }); + + self.rx.init(eth_dma); + self.tx.init(eth_dma); + + // Manage MAC transmission and reception + eth_mac.maccr.modify(|_, w| { + w.re().bit(true) // Receiver Enable + .te().bit(true) // Transmiter Enable + }); + eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit()); + + // Manage DMA transmission and reception + eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); + eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit()); + + eth_dma.dmacsr.modify(|_, w| + w.tps().set_bit() + .rps().set_bit() + ); } } @@ -590,8 +558,7 @@ impl<'a> phy::TxToken for TxToken<'a> { } } -pub unsafe fn interrupt_handler() { - let eth_dma = &*stm32::ETHERNET_DMA::ptr(); +pub unsafe fn interrupt_handler(eth_dma: &pac::ETHERNET_DMA) { eth_dma.dmacsr.write(|w| w .nis().set_bit() @@ -600,8 +567,7 @@ pub unsafe fn interrupt_handler() { ); } -pub unsafe fn enable_interrupt() { - let eth_dma = &*stm32::ETHERNET_DMA::ptr(); +pub unsafe fn enable_interrupt(eth_dma: &pac::ETHERNET_DMA) { eth_dma.dmacier.modify(|_, w| w .nie().set_bit() diff --git a/src/main.rs b/src/main.rs index 2997d71..37faf99 100644 --- a/src/main.rs +++ b/src/main.rs @@ -3,9 +3,17 @@ #![feature(asm)] // Enable returning `!` #![feature(never_type)] +#![feature(core_intrinsics)] +#[inline(never)] +#[panic_handler] #[cfg(not(feature = "semihosting"))] -extern crate panic_abort; +fn panic(_info: &core::panic::PanicInfo) -> ! { + let gpiod = unsafe { &*pac::GPIOD::ptr() }; + gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3 + unsafe { core::intrinsics::abort(); } +} + #[cfg(feature = "semihosting")] extern crate panic_semihosting; @@ -13,17 +21,15 @@ extern crate panic_semihosting; extern crate log; use core::ptr; -use core::cell::RefCell; -use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; +// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; use core::fmt::Write; -use cortex_m_rt::{entry, exception}; -use stm32h7::stm32h7x3::{self as stm32, Peripherals, CorePeripherals, interrupt}; -use cortex_m::interrupt::Mutex; +use cortex_m_rt::exception; +use stm32h7::stm32h743 as pac; use heapless::{String, Vec, consts::*}; use smoltcp as net; -use serde::{Serialize, Deserialize}; +use serde::{Serialize, Deserialize, de::DeserializeOwned}; use serde_json_core::{ser::to_string, de::from_slice}; mod eth; @@ -37,7 +43,7 @@ fn init_log() {} #[cfg(feature = "semihosting")] fn init_log() { use log::LevelFilter; - use cortex_m_log::log::{Logger, init}; + use cortex_m_log::log::{Logger, init as init_log}; use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout}; static mut LOGGER: Option>> = None; let logger = Logger { @@ -48,7 +54,7 @@ fn init_log() { LOGGER.get_or_insert(logger) }; - init(logger).unwrap(); + init_log(logger).unwrap(); } // Pull in build information (from `built` crate) @@ -57,10 +63,10 @@ mod build_info { // include!(concat!(env!("OUT_DIR"), "/built.rs")); } -fn pwr_setup(pwr: &stm32::PWR) { +fn pwr_setup(pwr: &pac::PWR) { // go to VOS1 voltage scale for high perf pwr.cr3.write(|w| - w.sden().set_bit() + w.scuen().set_bit() .ldoen().set_bit() .bypass().clear_bit() ); @@ -69,7 +75,7 @@ fn pwr_setup(pwr: &stm32::PWR) { while pwr.d3cr.read().vosrdy().bit_is_clear() {} } -fn rcc_reset(rcc: &stm32::RCC) { +fn rcc_reset(rcc: &pac::RCC) { // Reset all peripherals rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); rcc.ahb1rstr.write(|w| unsafe { w.bits(0)}); @@ -95,48 +101,44 @@ fn rcc_reset(rcc: &stm32::RCC) { rcc.apb4rstr.write(|w| unsafe { w.bits(0)}); } -fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { - // Ensure HSI is on and stable - rcc.cr.modify(|_, w| w.hsion().set_bit()); - while rcc.cr.read().hsirdy().bit_is_clear() {} - - // Set system clock to HSI - rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0) }); // hsi - while rcc.cfgr.read().sws().bits() != 0 {} - - // Clear registers to reset value - rcc.cr.write(|w| w.hsion().set_bit()); +fn rcc_pll_setup(rcc: &pac::RCC, flash: &pac::FLASH) { + // Switch to HSI to mess with HSE + rcc.cr.modify(|_, w| w.hsion().on()); + while rcc.cr.read().hsirdy().is_not_ready() {} + rcc.cfgr.modify(|_, w| w.sw().hsi()); + while !rcc.cfgr.read().sws().is_hsi() {} + rcc.cr.write(|w| w.hsion().on()); rcc.cfgr.reset(); // Ensure HSE is on and stable rcc.cr.modify(|_, w| - w.hseon().set_bit() - .hsebyp().clear_bit()); - while rcc.cr.read().hserdy().bit_is_clear() {} + w.hseon().on() + .hsebyp().not_bypassed()); + while !rcc.cr.read().hserdy().is_ready() {} - rcc.pllckselr.modify(|_, w| unsafe { - w.pllsrc().bits(0b10) // hse + rcc.pllckselr.modify(|_, w| + w.pllsrc().hse() .divm1().bits(1) // ref prescaler .divm2().bits(1) // ref prescaler - }); + ); // Configure PLL1: 8MHz /1 *100 /2 = 400 MHz - rcc.pllcfgr.modify(|_, w| unsafe { - w.pll1vcosel().clear_bit() // 192-836 MHz VCO - .pll1rge().bits(0b11) // 8-16 MHz PFD - .pll1fracen().clear_bit() - .divp1en().set_bit() - .pll2vcosel().set_bit() // 150-420 MHz VCO - .pll2rge().bits(0b11) // 8-16 MHz PFD - .pll2fracen().clear_bit() - .divp2en().set_bit() - .divq2en().set_bit() - }); + rcc.pllcfgr.modify(|_, w| + w.pll1vcosel().wide_vco() // 192-836 MHz VCO + .pll1rge().range8() // 8-16 MHz PFD + .pll1fracen().reset() + .divp1en().enabled() + .pll2vcosel().medium_vco() // 150-420 MHz VCO + .pll2rge().range8() // 8-16 MHz PFD + .pll2fracen().reset() + .divp2en().enabled() + .divq2en().enabled() + ); rcc.pll1divr.write(|w| unsafe { w.divn1().bits(100 - 1) // feebdack divider - .divp1().bits(2 - 1) // p output divider + .divp1().div2() // p output divider }); - rcc.cr.modify(|_, w| w.pll1on().set_bit()); - while rcc.cr.read().pll1rdy().bit_is_clear() {} + rcc.cr.modify(|_, w| w.pll1on().on()); + while !rcc.cr.read().pll1rdy().is_ready() {} // Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz rcc.pll2divr.write(|w| unsafe { @@ -144,24 +146,22 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { .divp1().bits(2 - 1) // p output divider .divq1().bits(2 - 1) // q output divider }); - rcc.cr.modify(|_, w| w.pll2on().set_bit()); - while rcc.cr.read().pll2rdy().bit_is_clear() {} + rcc.cr.modify(|_, w| w.pll2on().on()); + while !rcc.cr.read().pll2rdy().is_ready() {} // hclk 200 MHz, pclk 100 MHz - let dapb = 0b100; - rcc.d1cfgr.write(|w| unsafe { - w.d1cpre().bits(0) // sys_ck not divided - .hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2 - .d1ppre().bits(dapb) // rcc_pclk3 = rcc_hclk3 / 2 - }); - rcc.d2cfgr.write(|w| unsafe { - w.d2ppre1().bits(dapb) // rcc_pclk1 = rcc_hclk3 / 2 - .d2ppre2().bits(dapb) // rcc_pclk2 = rcc_hclk3 / 2 - - }); - rcc.d3cfgr.write(|w| unsafe { - w.d3ppre().bits(dapb) // rcc_pclk4 = rcc_hclk3 / 2 - }); + rcc.d1cfgr.write(|w| + w.d1cpre().div1() // sys_ck not divided + .hpre().div2() // rcc_hclk3 = sys_d1cpre_ck / 2 + .d1ppre().div2() // rcc_pclk3 = rcc_hclk3 / 2 + ); + rcc.d2cfgr.write(|w| + w.d2ppre1().div2() // rcc_pclk1 = rcc_hclk3 / 2 + .d2ppre2().div2() // rcc_pclk2 = rcc_hclk3 / 2 + ); + rcc.d3cfgr.write(|w| + w.d3ppre().div2() // rcc_pclk4 = rcc_hclk3 / 2 + ); // 2 wait states, 0b10 programming delay // 185-210 MHz @@ -172,27 +172,22 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { while flash.acr.read().latency().bits() != 2 {} // CSI for I/O compensationc ell - rcc.cr.modify(|_, w| w.csion().set_bit()); - while rcc.cr.read().csirdy().bit_is_clear() {} + rcc.cr.modify(|_, w| w.csion().on()); + while !rcc.cr.read().csirdy().is_ready() {} // Set system clock to pll1_p - rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p - while rcc.cfgr.read().sws().bits() != 0b011 {} + rcc.cfgr.modify(|_, w| w.sw().pll1()); + while !rcc.cfgr.read().sws().is_pll1() {} - rcc.d1ccipr.write(|w| unsafe { - w.ckpersrc().bits(1) // hse_ck - }); - rcc.d2ccip1r.modify(|_, w| unsafe { - w.spi123src().bits(1) // pll2_p - .spi45src().bits(1) // pll2_q - }); - - rcc.d3ccipr.modify(|_, w| unsafe { - w.spi6src().bits(1) // pll2_q - }); + rcc.d1ccipr.write(|w| w.ckpersel().hse()); + rcc.d2ccip1r.modify(|_, w| + w.spi123sel().pll2_p() + .spi45sel().pll2_q() + ); + rcc.d3ccipr.modify(|_, w| w.spi6sel().pll2_q()); } -fn io_compensation_setup(syscfg: &stm32::SYSCFG) { +fn io_compensation_setup(syscfg: &pac::SYSCFG) { syscfg.cccsr.modify(|_, w| w.en().set_bit() .cs().clear_bit() @@ -201,27 +196,27 @@ fn io_compensation_setup(syscfg: &stm32::SYSCFG) { while syscfg.cccsr.read().ready().bit_is_clear() {} } -fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, - gpioe: &stm32::GPIOE, gpiof: &stm32::GPIOF, gpiog: &stm32::GPIOG) { +fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, + gpioe: &pac::GPIOE, gpiof: &pac::GPIOF, gpiog: &pac::GPIOG) { // FP_LED0 gpiod.otyper.modify(|_, w| w.ot5().push_pull()); gpiod.moder.modify(|_, w| w.moder5().output()); - gpiod.odr.modify(|_, w| w.odr5().clear_bit()); + gpiod.odr.modify(|_, w| w.odr5().low()); // FP_LED1 gpiod.otyper.modify(|_, w| w.ot6().push_pull()); gpiod.moder.modify(|_, w| w.moder6().output()); - gpiod.odr.modify(|_, w| w.odr6().clear_bit()); + gpiod.odr.modify(|_, w| w.odr6().low()); // LED_FP2 gpiog.otyper.modify(|_, w| w.ot4().push_pull()); gpiog.moder.modify(|_, w| w.moder4().output()); - gpiog.odr.modify(|_, w| w.odr4().clear_bit()); + gpiog.odr.modify(|_, w| w.odr4().low()); // LED_FP3 gpiod.otyper.modify(|_, w| w.ot12().push_pull()); gpiod.moder.modify(|_, w| w.moder12().output()); - gpiod.odr.modify(|_, w| w.odr12().clear_bit()); + gpiod.odr.modify(|_, w| w.odr12().low()); // AFE0_A0,1: PG2,PG3 gpiog.otyper.modify(|_, w| @@ -233,8 +228,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, .moder3().output() ); gpiog.odr.modify(|_, w| - w.odr2().clear_bit() - .odr3().clear_bit() + w.odr2().low() + .odr3().low() ); // ADC0 @@ -274,12 +269,12 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, // DAC0_LDAC: PE11 gpioe.moder.modify(|_, w| w.moder11().output()); gpioe.otyper.modify(|_, w| w.ot11().push_pull()); - gpioe.odr.modify(|_, w| w.odr11().clear_bit()); + gpioe.odr.modify(|_, w| w.odr11().low()); // DAC_CLR: PE12 gpioe.moder.modify(|_, w| w.moder12().output()); gpioe.otyper.modify(|_, w| w.ot12().push_pull()); - gpioe.odr.modify(|_, w| w.odr12().set_bit()); + gpioe.odr.modify(|_, w| w.odr12().high()); // AFE1_A0,1: PD14,PD15 gpiod.otyper.modify(|_, w| @@ -291,8 +286,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, .moder15().output() ); gpiod.odr.modify(|_, w| - w.odr14().clear_bit() - .odr15().clear_bit() + w.odr14().low() + .odr15().low() ); // ADC1 @@ -332,127 +327,121 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, // DAC1_LDAC: PE15 gpioe.moder.modify(|_, w| w.moder15().output()); gpioe.otyper.modify(|_, w| w.ot15().push_pull()); - gpioe.odr.modify(|_, w| w.odr15().clear_bit()); + gpioe.odr.modify(|_, w| w.odr15().low()); } // ADC0 -fn spi1_setup(spi1: &stm32::SPI1) { - spi1.cfg1.modify(|_, w| { - w.mbr().bits(1) // clk/4 +fn spi1_setup(spi1: &pac::SPI1) { + spi1.cfg1.modify(|_, w| + w.mbr().div4() .dsize().bits(16 - 1) - .fthvl().one_frame() - }); - spi1.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().set_bit() - .cpha().set_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b10) // simplex receiver - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(6) // master SS idle - }); - spi1.cr2.modify(|_, w| { - w.tsize().bits(1) - }); - spi1.cr1.write(|w| w.spe().set_bit()); + .fthlv().one_frame() + ); + spi1.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_high() + .cpha().second_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().receiver() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(6) + ); + spi1.cr2.modify(|_, w| w.tsize().bits(1)); + spi1.cr1.write(|w| w.spe().enabled()); } // ADC1 -fn spi5_setup(spi5: &stm32::SPI5) { - spi5.cfg1.modify(|_, w| { - w.mbr().bits(1) // clk/4 +fn spi5_setup(spi5: &pac::SPI5) { + spi5.cfg1.modify(|_, w| + w.mbr().div4() .dsize().bits(16 - 1) - .fthvl().one_frame() - }); - spi5.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().set_bit() - .cpha().set_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b10) // simplex receiver - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(6) // master SS idle - }); - spi5.cr2.modify(|_, w| { - w.tsize().bits(1) - }); - spi5.cr1.write(|w| w.spe().set_bit()); + .fthlv().one_frame() + ); + spi5.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_high() + .cpha().second_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().receiver() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(6) + ); + spi5.cr2.modify(|_, w| w.tsize().bits(1)); + spi5.cr1.write(|w| w.spe().enabled()); } // DAC0 -fn spi2_setup(spi2: &stm32::SPI2) { - spi2.cfg1.modify(|_, w| { - w.mbr().bits(0) // clk/2 +fn spi2_setup(spi2: &pac::SPI2) { + spi2.cfg1.modify(|_, w| + w.mbr().div2() .dsize().bits(16 - 1) - .fthvl().one_frame() - }); - spi2.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().clear_bit() - .cpha().clear_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b01) // simplex transmitter - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(0) // master SS idle - }); + .fthlv().one_frame() + ); + spi2.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_low() + .cpha().first_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().transmitter() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(0) + ); spi2.cr2.modify(|_, w| w.tsize().bits(0)); spi2.cr1.write(|w| w.spe().enabled()); spi2.cr1.modify(|_, w| w.cstart().started()); } // DAC1 -fn spi4_setup(spi4: &stm32::SPI4) { - spi4.cfg1.modify(|_, w| { - w.mbr().bits(0) // clk/2 +fn spi4_setup(spi4: &pac::SPI4) { + spi4.cfg1.modify(|_, w| + w.mbr().div2() .dsize().bits(16 - 1) - .fthvl().one_frame() - }); - spi4.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().clear_bit() - .cpha().clear_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b01) // simplex transmitter - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(0) // master SS idle - }); - spi4.cr2.modify(|_, w| { - w.tsize().bits(0) - }); + .fthlv().one_frame() + ); + spi4.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_low() + .cpha().first_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().transmitter() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(0) + ); + spi4.cr2.modify(|_, w| w.tsize().bits(0)); spi4.cr1.write(|w| w.spe().enabled()); spi4.cr1.modify(|_, w| w.cstart().started()); } -fn tim2_setup(tim2: &stm32::TIM2) { - tim2.psc.write(|w| unsafe { w.psc().bits(200 - 1) }); // from 200 MHz +fn tim2_setup(tim2: &pac::TIM2) { + tim2.psc.write(|w| w.psc().bits(200 - 1)); // from 200 MHz tim2.arr.write(|w| unsafe { w.bits(2 - 1) }); // µs tim2.dier.write(|w| w.ude().set_bit()); tim2.egr.write(|w| w.ug().set_bit()); @@ -461,15 +450,15 @@ fn tim2_setup(tim2: &stm32::TIM2) { .cen().set_bit()); // enable } -fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { - dma1.s0cr.modify(|_, w| w.en().clear_bit()); - while dma1.s0cr.read().en().bit_is_set() {} +fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { + dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); + while dma1.st[0].cr.read().en().bit_is_set() {} - dma1.s0par.write(|w| unsafe { w.pa().bits(pa0 as u32) }); - dma1.s0m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); - dma1.s0ndtr.write(|w| unsafe { w.ndt().bits(1) }); - dmamux1.ccr[0].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up - dma1.s0cr.modify(|_, w| unsafe { + dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) }); + dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) }); + dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) }); + dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up()); + dma1.st[0].cr.modify(|_, w| unsafe { w.pl().bits(0b01) // medium .circ().set_bit() // reload ndtr .msize().bits(0b10) // 32 @@ -482,17 +471,17 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz .dir().bits(0b01) // memory_to_peripheral .pfctrl().clear_bit() // dma is FC }); - dma1.s0fcr.modify(|_, w| w.dmdis().clear_bit()); - dma1.s0cr.modify(|_, w| w.en().set_bit()); + dma1.st[0].fcr.modify(|_, w| w.dmdis().clear_bit()); + dma1.st[0].cr.modify(|_, w| w.en().set_bit()); - dma1.s1cr.modify(|_, w| w.en().clear_bit()); - while dma1.s1cr.read().en().bit_is_set() {} + dma1.st[1].cr.modify(|_, w| w.en().clear_bit()); + while dma1.st[1].cr.read().en().bit_is_set() {} - dma1.s1par.write(|w| unsafe { w.pa().bits(pa1 as u32) }); - dma1.s1m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); - dma1.s1ndtr.write(|w| unsafe { w.ndt().bits(1) }); - dmamux1.ccr[1].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up - dma1.s1cr.modify(|_, w| unsafe { + dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) }); + dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) }); + dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) }); + dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up()); + dma1.st[1].cr.modify(|_, w| unsafe { w.pl().bits(0b01) // medium .circ().set_bit() // reload ndtr .msize().bits(0b10) // 32 @@ -505,21 +494,16 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz .dir().bits(0b01) // memory_to_peripheral .pfctrl().clear_bit() // dma is FC }); - dma1.s1fcr.modify(|_, w| w.dmdis().clear_bit()); - dma1.s1cr.modify(|_, w| w.en().set_bit()); + dma1.st[1].fcr.modify(|_, w| w.dmdis().clear_bit()); + dma1.st[1].cr.modify(|_, w| w.en().set_bit()); } -type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>; -static SPIP: Mutex> = Mutex::new(RefCell::new(None)); +const SCALE: f32 = ((1 << 15) - 1) as f32; #[link_section = ".sram1.datspi"] static mut DAT: u32 = 0x201; // EN | CSTART -static TIME: AtomicU32 = AtomicU32::new(0); -static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); - -#[link_section = ".sram3.eth"] -static mut ETHERNET: eth::Device = eth::Device::new(); +// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); const TCP_RX_BUFFER_SIZE: usize = 8192; const TCP_TX_BUFFER_SIZE: usize = 8192; @@ -535,154 +519,254 @@ macro_rules! create_socket { ) } +#[rtfm::app(device = stm32h7::stm32h743)] +const APP: () = { + static SPI: (pac::SPI1, pac::SPI2, pac::SPI4, pac::SPI5) = (); + static ETHERNET_PERIPH: (pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL) = (); -#[entry] -fn main() -> ! { - let mut cp = CorePeripherals::take().unwrap(); - let dp = Peripherals::take().unwrap(); + static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2]; + static mut IIR_CH: [IIR; 2] = [ + IIR { + ba: [0., 0., 0., 0., 0.], + y_offset: 0., + y_min: -SCALE - 1., + y_max: SCALE + }; + 2]; - let rcc = dp.RCC; - rcc_reset(&rcc); + #[link_section = ".sram3.eth"] + static mut ETHERNET: eth::Device = eth::Device::new(); - init_log(); - // info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap()); - // info!("Built on {}", build_info::BUILT_TIME_UTC); - // info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET); + #[init(schedule = [tick])] + fn init(c: init::Context) -> init::LateResources { + let dp = c.device; + let cp = c.core; - pwr_setup(&dp.PWR); - rcc_pll_setup(&rcc, &dp.FLASH); - rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); - io_compensation_setup(&dp.SYSCFG); + let rcc = dp.RCC; + rcc_reset(&rcc); - // 100 MHz - cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core); - cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10); - cp.SYST.enable_counter(); - cp.SYST.enable_interrupt(); - unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority + init_log(); + // info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap()); + // info!("Built on {}", build_info::BUILT_TIME_UTC); + // info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET); - cp.SCB.enable_icache(); - // TODO: ETH DMA coherence issues - // cp.SCB.enable_dcache(&mut cp.CPUID); - cp.DWT.enable_cycle_counter(); + pwr_setup(&dp.PWR); + rcc_pll_setup(&rcc, &dp.FLASH); + rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); + io_compensation_setup(&dp.SYSCFG); - rcc.ahb4enr.modify(|_, w| - w.gpioaen().set_bit() - .gpioben().set_bit() - .gpiocen().set_bit() - .gpioden().set_bit() - .gpioeen().set_bit() - .gpiofen().set_bit() - .gpiogen().set_bit() - ); - gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOF, &dp.GPIOG); + cp.SCB.enable_icache(); + // TODO: ETH DMA coherence issues + // cp.SCB.enable_dcache(&mut cp.CPUID); + // cp.DWT.enable_cycle_counter(); - rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit()); - let spi2 = dp.SPI2; - spi2_setup(&spi2); + rcc.ahb4enr.modify(|_, w| + w.gpioaen().set_bit() + .gpioben().set_bit() + .gpiocen().set_bit() + .gpioden().set_bit() + .gpioeen().set_bit() + .gpiofen().set_bit() + .gpiogen().set_bit() + ); + gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOF, &dp.GPIOG); - rcc.apb2enr.modify(|_, w| w.spi4en().set_bit()); - let spi4 = dp.SPI4; - spi4_setup(&spi4); + rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit()); + let spi2 = dp.SPI2; + spi2_setup(&spi2); - rcc.apb2enr.modify(|_, w| w.spi1en().set_bit()); - let spi1 = dp.SPI1; - spi1_setup(&spi1); - spi1.ier.write(|w| w.eotie().set_bit()); + rcc.apb2enr.modify(|_, w| w.spi4en().set_bit()); + let spi4 = dp.SPI4; + spi4_setup(&spi4); - rcc.apb2enr.modify(|_, w| w.spi5en().set_bit()); - let spi5 = dp.SPI5; - spi5_setup(&spi5); - // spi5.ier.write(|w| w.eotie().set_bit()); + rcc.apb2enr.modify(|_, w| w.spi1en().set_bit()); + let spi1 = dp.SPI1; + spi1_setup(&spi1); + spi1.ier.write(|w| w.eotie().set_bit()); - rcc.ahb2enr.modify(|_, w| - w - .sram1en().set_bit() - .sram2en().set_bit() - .sram3en().set_bit() - ); - rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit()); - // init SRAM1 rodata can't load with sram1 disabled - unsafe { DAT = 0x201 }; // EN | CSTART - cortex_m::asm::dsb(); - let dat_addr = unsafe { &DAT as *const _ } as usize; - cp.SCB.clean_dcache_by_address(dat_addr, 4); + rcc.apb2enr.modify(|_, w| w.spi5en().set_bit()); + let spi5 = dp.SPI5; + spi5_setup(&spi5); + // spi5.ier.write(|w| w.eotie().set_bit()); - dma1_setup(&dp.DMA1, &dp.DMAMUX1, dat_addr, - &spi1.cr1 as *const _ as usize, - &spi5.cr1 as *const _ as usize); + rcc.ahb2enr.modify(|_, w| + w + .sram1en().set_bit() + .sram2en().set_bit() + .sram3en().set_bit() + ); + rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit()); + // init SRAM1 rodata can't load with sram1 disabled + unsafe { DAT = 0x201 }; // EN | CSTART + cortex_m::asm::dsb(); + let dat_addr = unsafe { &DAT as *const _ } as usize; + cp.SCB.clean_dcache_by_address(dat_addr, 4); - rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); + dma1_setup(&dp.DMA1, &dp.DMAMUX1, dat_addr, + &spi1.cr1 as *const _ as usize, + &spi5.cr1 as *const _ as usize); - // work around the SPI stall erratum - //let dbgmcu = dp.DBGMCU; - //dbgmcu.apb1lfz1.modify(|_, w| w.stop_tim2().set_bit()); // stop tim2 in debug - unsafe { ptr::write_volatile(0x5c00_103c as *mut usize, 0x0000_0001) }; + rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); - eth::setup(&rcc, &dp.SYSCFG); - eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); + // work around the SPI stall erratum + let dbgmcu = dp.DBGMCU; + dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit()); - let device = unsafe { &mut ETHERNET }; - let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); - unsafe { device.init(hardware_addr) }; - let mut neighbor_cache_storage = [None; 8]; - let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); - let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); - let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)]; - let mut iface = net::iface::EthernetInterfaceBuilder::new(device) - .ethernet_addr(hardware_addr) - .neighbor_cache(neighbor_cache) - .ip_addrs(&mut ip_addrs[..]) - .finalize(); - let mut socket_set_entries: [_; 8] = Default::default(); - let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); - create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); - create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); + tim2_setup(&dp.TIM2); - unsafe { eth::enable_interrupt(); } - unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio - cp.NVIC.enable(stm32::Interrupt::ETH); + eth::setup(&rcc, &dp.SYSCFG); + eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); - tim2_setup(&dp.TIM2); + // c.schedule.tick(rtfm::Instant::now()).unwrap(); - unsafe { cp.NVIC.set_priority(stm32::Interrupt::SPI1, 0); } // highest prio - cortex_m::interrupt::free(|cs| { - cp.NVIC.enable(stm32::Interrupt::SPI1); - SPIP.borrow(cs).replace(Some((spi1, spi2, spi4, spi5))); - }); - - let mut last = 0; - let mut server = Server::new(); - loop { - // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } - let time = TIME.load(Ordering::Relaxed); - { - let socket = &mut *sockets.get::(tcp_handle0); - if !(socket.is_open() || socket.is_listening()) { - socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else if last != time && socket.can_send() { - last = time; - handle_status(socket, time); - } - } - { - let socket = &mut *sockets.get::(tcp_handle1); - if !(socket.is_open() || socket.is_listening()) { - socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else { - server.handle_command(socket); - } - } - - if !match iface.poll(&mut sockets, net::time::Instant::from_millis(time as i64)) { - Ok(changed) => changed, - Err(net::Error::Unrecognized) => true, - Err(e) => { info!("iface poll error: {:?}", e); true } - } { - cortex_m::asm::wfi(); + init::LateResources { + SPI: (spi1, spi2, spi4, spi5), + ETHERNET_PERIPH: (dp.ETHERNET_MAC, dp.ETHERNET_DMA, dp.ETHERNET_MTL), } } -} + + #[idle(resources = [ETHERNET, ETHERNET_PERIPH, IIR_STATE, IIR_CH])] + fn idle(c: idle::Context) -> ! { + let (MAC, DMA, MTL) = c.resources.ETHERNET_PERIPH; + + let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); + unsafe { c.resources.ETHERNET.init(hardware_addr, MAC, DMA, MTL) }; + let mut neighbor_cache_storage = [None; 8]; + let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); + let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); + let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)]; + let mut iface = net::iface::EthernetInterfaceBuilder::new(c.resources.ETHERNET) + .ethernet_addr(hardware_addr) + .neighbor_cache(neighbor_cache) + .ip_addrs(&mut ip_addrs[..]) + .finalize(); + let mut socket_set_entries: [_; 8] = Default::default(); + let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); + create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); + create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); + + // unsafe { eth::enable_interrupt(DMA); } + let mut time = 0u32; + let mut next_ms = rtfm::Instant::now(); + next_ms += 200_000.cycles(); + let mut server = Server::new(); + let mut iir_state: resources::IIR_STATE = c.resources.IIR_STATE; + let mut iir_ch: resources::IIR_CH = c.resources.IIR_CH; + loop { + // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } + let tick = rtfm::Instant::now() > next_ms; + if tick { + next_ms += 200_000.cycles(); + time += 1; + } + { + let socket = &mut *sockets.get::(tcp_handle0); + if socket.state() == net::socket::TcpState::CloseWait { + socket.close(); + } else if !(socket.is_open() || socket.is_listening()) { + socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); + } else if tick && socket.can_send() { + let s = iir_state.lock(|iir_state| Status { + t: time, + x0: iir_state[0][0], + y0: iir_state[0][2], + x1: iir_state[1][0], + y1: iir_state[1][2] + }); + json_reply(socket, &s); + } + } + { + let socket = &mut *sockets.get::(tcp_handle1); + if socket.state() == net::socket::TcpState::CloseWait { + socket.close(); + } else if !(socket.is_open() || socket.is_listening()) { + socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); + } else { + server.poll(socket, |req: &Request| { + if req.channel < 2 { + iir_ch.lock(|iir_ch| iir_ch[req.channel as usize] = req.iir); + } + }); + } + } + + if !match iface.poll(&mut sockets, net::time::Instant::from_millis(time as i64)) { + Ok(changed) => changed, + Err(net::Error::Unrecognized) => true, + Err(e) => { info!("iface poll error: {:?}", e); true } + } { + // cortex_m::asm::wfi(); + } + } + } + + #[task(priority = 1, schedule = [tick])] + fn tick(c: tick::Context) { + static mut TIME: u32 = 0; + *TIME += 1; + const PERIOD: u32 = 200_000_000; + c.schedule.tick(c.scheduled + PERIOD.cycles()).unwrap(); + } + + // seems to slow it down + // #[link_section = ".data.spi1"] + #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 2)] + fn SPI1(c: SPI1::Context) { + #[cfg(feature = "bkpt")] + cortex_m::asm::bkpt(); + let (spi1, spi2, spi4, spi5) = c.resources.SPI; + let iir_ch = c.resources.IIR_CH; + let mut iir_state = c.resources.IIR_STATE; + + let sr = spi1.sr.read(); + if sr.eot().bit_is_set() { + spi1.ifcr.write(|w| w.eotc().set_bit()); + } + if sr.rxp().bit_is_set() { + let rxdr = &spi1.rxdr as *const _ as *const u16; + let a = unsafe { ptr::read_volatile(rxdr) }; + let x0 = f32::from(a as i16); + let y0 = iir_ch[0].update(&mut iir_state[0], x0); + let d = y0 as i16 as u16 ^ 0x8000; + let txdr = &spi2.txdr as *const _ as *mut u16; + unsafe { ptr::write_volatile(txdr, d) }; + } + + let sr = spi5.sr.read(); + if sr.eot().bit_is_set() { + spi5.ifcr.write(|w| w.eotc().set_bit()); + } + if sr.rxp().bit_is_set() { + let rxdr = &spi5.rxdr as *const _ as *const u16; + let a = unsafe { ptr::read_volatile(rxdr) }; + let x0 = f32::from(a as i16); + let y0 = iir_ch[1].update(&mut iir_state[1], x0); + let d = y0 as i16 as u16 ^ 0x8000; + let txdr = &spi4.txdr as *const _ as *mut u16; + unsafe { ptr::write_volatile(txdr, d) }; + } + #[cfg(feature = "bkpt")] + cortex_m::asm::bkpt(); + } + + /* + #[interrupt(resources = [ETHERNET_PERIPH], priority = 1)] + fn ETH(c: ETH::Context) { + let dma = &c.resources.ETHERNET_PERIPH.1; + ETHERNET_PENDING.store(true, Ordering::Relaxed); + unsafe { eth::interrupt_handler(dma) } + } + */ + + extern "C" { + // hw interrupt handlers for RTFM to use for scheduling tasks + // one per priority + fn DCMI(); + fn JPEG(); + fn SDMMC(); + } +}; #[derive(Deserialize,Serialize)] struct Request { @@ -696,7 +780,16 @@ struct Response<'a> { message: &'a str, } -fn reply(socket: &mut net::socket::TcpSocket, msg: &T) { +#[derive(Serialize)] +struct Status { + t: u32, + x0: f32, + y0: f32, + x1: f32, + y1: f32 +} + +fn json_reply(socket: &mut net::socket::TcpSocket, msg: &T) { let mut u: String = to_string(msg).unwrap(); u.push('\n').unwrap(); socket.write_str(&u).unwrap(); @@ -712,7 +805,11 @@ impl Server { Self { data: Vec::new(), discard: false } } - fn handle_command(&mut self, socket: &mut net::socket::TcpSocket) { + fn poll(&mut self, socket: &mut net::socket::TcpSocket, f: F) -> Option + where + T: DeserializeOwned, + F: FnOnce(&T) -> R, + { while socket.can_recv() { let found = socket.recv(|buf| { let (len, found) = match buf.iter().position(|&c| c as char == '\n') { @@ -727,116 +824,32 @@ impl Server { } (len, found) }).unwrap(); - if !found { - continue; - } - let resp = if self.discard { - self.discard = false; - Response{ code: 520, message: "command buffer overflow" } - } else { - match from_slice::(&self.data) { - Ok(request) => { - if request.channel > 1 { - Response{ code: 530, message: "invalid channel" } - } else { - cortex_m::interrupt::free(|_| { - unsafe { IIR_CH[request.channel as usize] = request.iir; }; - }); - Response{ code: 200, message: "ok" } - } - }, - Err(err) => { - warn!("parse error {:?}", err); - Response{ code: 550, message: "parse error" } - }, + if found { + if self.discard { + self.discard = false; + json_reply(socket, &Response { code: 520, message: "command buffer overflow" }); + self.data.clear(); + } else { + let r = from_slice::(&self.data); + self.data.clear(); + match r { + Ok(res) => { + let r = f(&res); + json_reply(socket, &Response { code: 200, message: "ok" }); + return Some(r); + }, + Err(err) => { + warn!("parse error {:?}", err); + json_reply(socket, &Response { code: 550, message: "parse error" }); + }, + } } - }; - self.data.clear(); - reply(socket, &resp); - socket.close(); + } } + None } } -fn handle_status(socket: &mut net::socket::TcpSocket, time: u32) { - let s = unsafe { Status{ - t: time, - x0: IIR_STATE[0][0], - y0: IIR_STATE[0][2], - x1: IIR_STATE[1][0], - y1: IIR_STATE[1][2], - }}; - reply(socket, &s); -} - -#[derive(Serialize)] -struct Status { - t: u32, - x0: f32, - y0: f32, - x1: f32, - y1: f32 -} - -const SCALE: f32 = ((1 << 15) - 1) as f32; -static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2]; -static mut IIR_CH: [IIR; 2] = [ - IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0., - y_min: -SCALE - 1., y_max: SCALE }; 2]; - -// seems to slow it down -// #[link_section = ".data.spi1"] -#[interrupt] -fn SPI1() { - #[cfg(feature = "bkpt")] - cortex_m::asm::bkpt(); - cortex_m::interrupt::free(|cs| { - let spip = SPIP.borrow(cs).borrow(); - let (spi1, spi2, spi4, spi5) = spip.as_ref().unwrap(); - - let sr = spi1.sr.read(); - if sr.eot().bit_is_set() { - spi1.ifcr.write(|w| w.eotc().set_bit()); - } - if sr.rxp().bit_is_set() { - let rxdr = &spi1.rxdr as *const _ as *const u16; - let a = unsafe { ptr::read_volatile(rxdr) }; - let x0 = f32::from(a as i16); - let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) }; - let d = y0 as i16 as u16 ^ 0x8000; - let txdr = &spi2.txdr as *const _ as *mut u16; - unsafe { ptr::write_volatile(txdr, d) }; - } - - let sr = spi5.sr.read(); - if sr.eot().bit_is_set() { - spi5.ifcr.write(|w| w.eotc().set_bit()); - } - if sr.rxp().bit_is_set() { - let rxdr = &spi5.rxdr as *const _ as *const u16; - let a = unsafe { ptr::read_volatile(rxdr) }; - let x0 = f32::from(a as i16); - let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) }; - let d = y0 as i16 as u16 ^ 0x8000; - let txdr = &spi4.txdr as *const _ as *mut u16; - unsafe { ptr::write_volatile(txdr, d) }; - } - }); - #[cfg(feature = "bkpt")] - cortex_m::asm::bkpt(); -} - -#[interrupt] -fn ETH() { - ETHERNET_PENDING.store(true, Ordering::Relaxed); - unsafe { eth::interrupt_handler() } -} - -#[exception] -fn SysTick() { - TIME.fetch_add(1, Ordering::Relaxed); -} - #[exception] fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { panic!("HardFault at {:#?}", ef);