From 23e262304bf27faf99a9733b90e4720313463fd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 6 May 2019 08:47:49 +0000 Subject: [PATCH 01/21] stm32h7 changes round 1 --- src/main.rs | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/main.rs b/src/main.rs index 95eb517..6930f74 100644 --- a/src/main.rs +++ b/src/main.rs @@ -336,7 +336,7 @@ fn spi1_setup(spi1: &stm32::SPI1) { spi1.cfg1.modify(|_, w| { w.mbr().bits(1) // clk/4 .dsize().bits(16 - 1) - .fthvl().one_frame() + .fthlv().one_frame() }); spi1.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -365,7 +365,7 @@ fn spi5_setup(spi5: &stm32::SPI5) { spi5.cfg1.modify(|_, w| { w.mbr().bits(1) // clk/4 .dsize().bits(16 - 1) - .fthvl().one_frame() + .fthlv().one_frame() }); spi5.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -394,7 +394,7 @@ fn spi2_setup(spi2: &stm32::SPI2) { spi2.cfg1.modify(|_, w| { w.mbr().bits(0) // clk/2 .dsize().bits(16 - 1) - .fthvl().one_frame() + .fthlv().one_frame() }); spi2.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -422,7 +422,7 @@ fn spi4_setup(spi4: &stm32::SPI4) { spi4.cfg1.modify(|_, w| { w.mbr().bits(0) // clk/2 .dsize().bits(16 - 1) - .fthvl().one_frame() + .fthlv().one_frame() }); spi4.cfg2.modify(|_, w| unsafe { w.afcntr().set_bit() @@ -458,14 +458,14 @@ fn tim2_setup(tim2: &stm32::TIM2) { } fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { - dma1.s0cr.modify(|_, w| w.en().clear_bit()); - while dma1.s0cr.read().en().bit_is_set() {} + dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); + while dma1.st[0].cr.read().en().bit_is_set() {} - dma1.s0par.write(|w| unsafe { w.pa().bits(pa0 as u32) }); - dma1.s0m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); - dma1.s0ndtr.write(|w| unsafe { w.ndt().bits(1) }); + dma1.st[0].par.write(|w| unsafe { w.pa().bits(pa0 as u32) }); + dma1.st[0].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); + dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) }); dmamux1.ccr[0].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up - dma1.s0cr.modify(|_, w| unsafe { + dma1.st[0].cr.modify(|_, w| unsafe { w.pl().bits(0b01) // medium .circ().set_bit() // reload ndtr .msize().bits(0b10) // 32 @@ -478,17 +478,17 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz .dir().bits(0b01) // memory_to_peripheral .pfctrl().clear_bit() // dma is FC }); - dma1.s0fcr.modify(|_, w| w.dmdis().clear_bit()); - dma1.s0cr.modify(|_, w| w.en().set_bit()); + dma1.st[0].fcr.modify(|_, w| w.dmdis().clear_bit()); + dma1.st[0].cr.modify(|_, w| w.en().set_bit()); - dma1.s1cr.modify(|_, w| w.en().clear_bit()); - while dma1.s1cr.read().en().bit_is_set() {} + dma1.st[1].cr.modify(|_, w| w.en().clear_bit()); + while dma1.st[1].cr.read().en().bit_is_set() {} - dma1.s1par.write(|w| unsafe { w.pa().bits(pa1 as u32) }); - dma1.s1m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); - dma1.s1ndtr.write(|w| unsafe { w.ndt().bits(1) }); + dma1.st[1].par.write(|w| unsafe { w.pa().bits(pa1 as u32) }); + dma1.st[1].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); + dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) }); dmamux1.ccr[1].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up - dma1.s1cr.modify(|_, w| unsafe { + dma1.st[1].cr.modify(|_, w| unsafe { w.pl().bits(0b01) // medium .circ().set_bit() // reload ndtr .msize().bits(0b10) // 32 @@ -501,8 +501,8 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz .dir().bits(0b01) // memory_to_peripheral .pfctrl().clear_bit() // dma is FC }); - dma1.s1fcr.modify(|_, w| w.dmdis().clear_bit()); - dma1.s1cr.modify(|_, w| w.en().set_bit()); + dma1.st[1].fcr.modify(|_, w| w.dmdis().clear_bit()); + dma1.st[1].cr.modify(|_, w| w.en().set_bit()); } type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>; From 61adbd8c9e59d821e4d631707ca4e7656b707d5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 6 May 2019 08:48:05 +0000 Subject: [PATCH 02/21] new stm32h7 pac --- Cargo.lock | 4 +--- Cargo.toml | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 7cb4aa5..8a373fd 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -303,7 +303,7 @@ dependencies = [ "panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)", "panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)", "smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", - "stm32h7 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)", + "stm32h7 0.7.0", ] [[package]] @@ -314,7 +314,6 @@ source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "stm32h7" version = "0.7.0" -source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -464,7 +463,6 @@ source = "registry+https://github.com/rust-lang/crates.io-index" "checksum smallvec 0.6.9 (registry+https://github.com/rust-lang/crates.io-index)" = "c4488ae950c49d403731982257768f48fada354a5203fe81f9bb6f43ca9002be" "checksum smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fef582369edb298c6c41319a544ca9c4e83622f226055ccfcb35974fbb55ed34" "checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" -"checksum stm32h7 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "64173a3f8edb1bf9e17b14861695da2a7e6ca98afc99e0f249b62e4962cc478d" "checksum syn 0.15.33 (registry+https://github.com/rust-lang/crates.io-index)" = "ec52cd796e5f01d0067225a5392e70084acc4c0013fa71d55166d38a8b307836" "checksum time 0.1.42 (registry+https://github.com/rust-lang/crates.io-index)" = "db8dcfca086c1143c9270ac42a2bbd8a7ee477b78ac8e45b19abfb0cbede4b6f" "checksum toml 0.4.10 (registry+https://github.com/rust-lang/crates.io-index)" = "758664fc71a3a69038656bee8b6be6477d2a6c315a6b81f7081f591bffa4111f" diff --git a/Cargo.toml b/Cargo.toml index e895cf9..b5e388f 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -30,7 +30,7 @@ default-target = "thumbv7em-none-eabihf" cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] } cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-log = { version = "0.5", features = ["log-integration"] } -stm32h7 = { version = "0.7", features = ["stm32h7x3", "rt"] } +stm32h7 = { path = "../stm32-rs/stm32h7", features = ["stm32h7x3", "rt"] } log = "0.4" panic-abort = "0.3" panic-semihosting = { version = "0.5.2", optional = true } From 86dbdf98e2f716998a0495f732e727daedf60e61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 6 May 2019 08:48:22 +0000 Subject: [PATCH 03/21] stm32h7 svd and pac changes --- src/eth.rs | 16 ++++++---------- src/main.rs | 2 +- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/eth.rs b/src/eth.rs index 7761817..4b12e4c 100644 --- a/src/eth.rs +++ b/src/eth.rs @@ -360,7 +360,6 @@ impl Device { cortex_m::interrupt::free(|_cs| { let eth_mac = &*stm32::ETHERNET_MAC::ptr(); let eth_dma = &*stm32::ETHERNET_DMA::ptr(); - let _eth_mmc = &*stm32::ETHERNET_MMC::ptr(); let eth_mtl = &*stm32::ETHERNET_MTL::ptr(); eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); @@ -407,9 +406,6 @@ impl Device { eth_mac.maca0hr.write(|w| w.addrhi().bits( u16::from(mac.0[4]) | (u16::from(mac.0[5]) << 8)) - .ae().set_bit() - //.sa().clear_bit() - //.mbc().bits(0b000000) ); // frame filter register eth_mac.macpfr.modify(|_, w| { @@ -433,12 +429,12 @@ impl Device { }); eth_mac.macwtr.write(|w| w.pwe().clear_bit()); // Flow Control Register - eth_mac.macqtxfcr.modify(|_, w| { + eth_mac.macqtx_fcr.modify(|_, w| { // Pause time w.pt().bits(0x100) }); - eth_mac.macrxfcr.modify(|_, w| w); - eth_mtl.mtlrxqomr.modify(|_, w| + eth_mac.macrx_fcr.modify(|_, w| w); + eth_mtl.mtlrx_qomr.modify(|_, w| w // Receive store and forward .rsf().set_bit() @@ -449,7 +445,7 @@ impl Device { // Forward undersized good packets .fup().clear_bit() ); - eth_mtl.mtltxqomr.modify(|_, w| { + eth_mtl.mtltx_qomr.modify(|_, w| { w // Transmit store and forward .tsf().set_bit() @@ -473,7 +469,7 @@ impl Device { // operation mode register eth_dma.dmamr.modify(|_, w| { w - .intm().clear_bit() // FIXME: bits(0b00) + .intm().bits(0b00) // Rx Tx priority ratio 1:1 .pr().bits(0b000) .txpr().clear_bit() @@ -519,7 +515,7 @@ impl Device { w.re().bit(true) // Receiver Enable .te().bit(true) // Transmiter Enable }); - eth_mtl.mtltxqomr.modify(|_, w| w.ftq().set_bit()); + eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit()); // Manage DMA transmission and reception eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); diff --git a/src/main.rs b/src/main.rs index 6930f74..0d9a180 100644 --- a/src/main.rs +++ b/src/main.rs @@ -56,7 +56,7 @@ mod build_info { fn pwr_setup(pwr: &stm32::PWR) { // go to VOS1 voltage scale for high perf pwr.cr3.write(|w| - w.sden().set_bit() + w.scuen().set_bit() .ldoen().set_bit() .bypass().clear_bit() ); From f1c43c64928519545c27f3468e2d941326d9b857 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 6 May 2019 17:09:49 +0000 Subject: [PATCH 04/21] pac updates (~0.8) --- Cargo.toml | 7 +- src/main.rs | 181 +++++++++++++++++++++++++--------------------------- 2 files changed, 92 insertions(+), 96 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index b5e388f..8626796 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -30,14 +30,17 @@ default-target = "thumbv7em-none-eabihf" cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] } cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-log = { version = "0.5", features = ["log-integration"] } -stm32h7 = { path = "../stm32-rs/stm32h7", features = ["stm32h7x3", "rt"] } log = "0.4" panic-abort = "0.3" panic-semihosting = { version = "0.5.2", optional = true } +[dependencies.stm32h7] +path = "../stm32-rs/stm32h7" +# version = "0.7" +features = ["stm32h7x3", "rt"] + [dependencies.smoltcp] #git = "https://github.com/m-labs/smoltcp" -#rev = "cd893e6" version = "0.5" features = ["proto-ipv4", "socket-tcp"] default-features = false diff --git a/src/main.rs b/src/main.rs index 0d9a180..1aeff42 100644 --- a/src/main.rs +++ b/src/main.rs @@ -333,85 +333,81 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, // ADC0 fn spi1_setup(spi1: &stm32::SPI1) { - spi1.cfg1.modify(|_, w| { - w.mbr().bits(1) // clk/4 + spi1.cfg1.modify(|_, w| + w.mbr().div4() .dsize().bits(16 - 1) .fthlv().one_frame() - }); - spi1.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().set_bit() - .cpha().set_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b10) // simplex receiver - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(6) // master SS idle - }); - spi1.cr2.modify(|_, w| { - w.tsize().bits(1) - }); + ); + spi1.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_high() + .cpha().second_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().receiver() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(6) + ); + spi1.cr2.modify(|_, w| w.tsize().bits(1)); spi1.cr1.write(|w| w.spe().set_bit()); } // ADC1 fn spi5_setup(spi5: &stm32::SPI5) { - spi5.cfg1.modify(|_, w| { - w.mbr().bits(1) // clk/4 + spi5.cfg1.modify(|_, w| + w.mbr().div4() .dsize().bits(16 - 1) .fthlv().one_frame() - }); - spi5.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().set_bit() - .cpha().set_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b10) // simplex receiver - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(6) // master SS idle - }); - spi5.cr2.modify(|_, w| { - w.tsize().bits(1) - }); + ); + spi5.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_high() + .cpha().second_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().receiver() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(6) + ); + spi5.cr2.modify(|_, w| w.tsize().bits(1)); spi5.cr1.write(|w| w.spe().set_bit()); } // DAC0 fn spi2_setup(spi2: &stm32::SPI2) { - spi2.cfg1.modify(|_, w| { - w.mbr().bits(0) // clk/2 + spi2.cfg1.modify(|_, w| + w.mbr().div2() .dsize().bits(16 - 1) .fthlv().one_frame() - }); - spi2.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().clear_bit() - .cpha().clear_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b01) // simplex transmitter - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(0) // master SS idle - }); + ); + spi2.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_low() + .cpha().first_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().transmitter() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(0) + ); spi2.cr2.modify(|_, w| w.tsize().bits(0)); spi2.cr1.write(|w| w.spe().enabled()); spi2.cr1.modify(|_, w| w.cstart().started()); @@ -419,30 +415,28 @@ fn spi2_setup(spi2: &stm32::SPI2) { // DAC1 fn spi4_setup(spi4: &stm32::SPI4) { - spi4.cfg1.modify(|_, w| { - w.mbr().bits(0) // clk/2 + spi4.cfg1.modify(|_, w| + w.mbr().div2() .dsize().bits(16 - 1) .fthlv().one_frame() - }); - spi4.cfg2.modify(|_, w| unsafe { - w.afcntr().set_bit() - .ssom().set_bit() // ss deassert between frames during midi - .ssoe().set_bit() // ss output enable - .ssiop().clear_bit() // ss active low - .ssm().clear_bit() // PAD counts - .cpol().clear_bit() - .cpha().clear_bit() - .lsbfrst().clear_bit() - .master().set_bit() - .sp().bits(0) // motorola - .comm().bits(0b01) // simplex transmitter - .ioswp().clear_bit() - .midi().bits(0) // master inter data idle - .mssi().bits(0) // master SS idle - }); - spi4.cr2.modify(|_, w| { - w.tsize().bits(0) - }); + ); + spi4.cfg2.modify(|_, w| + w.afcntr().controlled() + .ssom().not_asserted() + .ssoe().enabled() + .ssiop().active_low() + .ssm().disabled() + .cpol().idle_low() + .cpha().first_edge() + .lsbfrst().msbfirst() + .master().master() + .sp().motorola() + .comm().transmitter() + .ioswp().disabled() + .midi().bits(0) + .mssi().bits(0) + ); + spi4.cr2.modify(|_, w| w.tsize().bits(0)); spi4.cr1.write(|w| w.spe().enabled()); spi4.cr1.modify(|_, w| w.cstart().started()); } @@ -461,10 +455,10 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); while dma1.st[0].cr.read().en().bit_is_set() {} - dma1.st[0].par.write(|w| unsafe { w.pa().bits(pa0 as u32) }); - dma1.st[0].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); + dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) }); + dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) }); dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) }); - dmamux1.ccr[0].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up + dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up()); dma1.st[0].cr.modify(|_, w| unsafe { w.pl().bits(0b01) // medium .circ().set_bit() // reload ndtr @@ -484,10 +478,10 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz dma1.st[1].cr.modify(|_, w| w.en().clear_bit()); while dma1.st[1].cr.read().en().bit_is_set() {} - dma1.st[1].par.write(|w| unsafe { w.pa().bits(pa1 as u32) }); - dma1.st[1].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) }); + dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) }); + dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) }); dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) }); - dmamux1.ccr[1].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up + dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up()); dma1.st[1].cr.modify(|_, w| unsafe { w.pl().bits(0b01) // medium .circ().set_bit() // reload ndtr @@ -611,9 +605,8 @@ fn main() -> ! { rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); // work around the SPI stall erratum - //let dbgmcu = dp.DBGMCU; - //dbgmcu.apb1lfz1.modify(|_, w| w.stop_tim2().set_bit()); // stop tim2 in debug - unsafe { ptr::write_volatile(0x5c00_103c as *mut usize, 0x0000_0001) }; + let dbgmcu = dp.DBGMCU; + dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit()); unsafe { let t = 2e-6*2.; From bdb6955aa1988eea6cd3e48ab0376088c0cf7f3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 6 May 2019 18:10:25 +0000 Subject: [PATCH 05/21] pac: rcc --- src/main.rs | 111 +++++++++++++++++++++++----------------------------- 1 file changed, 50 insertions(+), 61 deletions(-) diff --git a/src/main.rs b/src/main.rs index 1aeff42..3ea48d9 100644 --- a/src/main.rs +++ b/src/main.rs @@ -92,47 +92,43 @@ fn rcc_reset(rcc: &stm32::RCC) { } fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { - // Ensure HSI is on and stable - rcc.cr.modify(|_, w| w.hsion().set_bit()); - while rcc.cr.read().hsirdy().bit_is_clear() {} - - // Set system clock to HSI - rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0) }); // hsi - while rcc.cfgr.read().sws().bits() != 0 {} - - // Clear registers to reset value - rcc.cr.write(|w| w.hsion().set_bit()); + // Switch to HSI to mess with HSE + rcc.cr.modify(|_, w| w.hsion().on()); + while rcc.cr.read().hsirdy().is_not_ready() {} + rcc.cfgr.modify(|_, w| w.sw().hsi()); + while !rcc.cfgr.read().sws().is_hsi() {} + rcc.cr.write(|w| w.hsion().on()); rcc.cfgr.reset(); // Ensure HSE is on and stable rcc.cr.modify(|_, w| - w.hseon().set_bit() - .hsebyp().clear_bit()); - while rcc.cr.read().hserdy().bit_is_clear() {} + w.hseon().on() + .hsebyp().not_bypassed()); + while !rcc.cr.read().hserdy().is_ready() {} - rcc.pllckselr.modify(|_, w| unsafe { - w.pllsrc().bits(0b10) // hse + rcc.pllckselr.modify(|_, w| + w.pllsrc().hse() .divm1().bits(1) // ref prescaler .divm2().bits(1) // ref prescaler - }); + ); // Configure PLL1: 8MHz /1 *100 /2 = 400 MHz - rcc.pllcfgr.modify(|_, w| unsafe { - w.pll1vcosel().clear_bit() // 192-836 MHz VCO - .pll1rge().bits(0b11) // 8-16 MHz PFD - .pll1fracen().clear_bit() - .divp1en().set_bit() - .pll2vcosel().set_bit() // 150-420 MHz VCO - .pll2rge().bits(0b11) // 8-16 MHz PFD - .pll2fracen().clear_bit() - .divp2en().set_bit() - .divq2en().set_bit() - }); + rcc.pllcfgr.modify(|_, w| + w.pll1vcosel().wide_vco() // 192-836 MHz VCO + .pll1rge().range8() // 8-16 MHz PFD + .pll1fracen().reset() + .divp1en().enabled() + .pll2vcosel().medium_vco() // 150-420 MHz VCO + .pll2rge().range8() // 8-16 MHz PFD + .pll2fracen().reset() + .divp2en().enabled() + .divq2en().enabled() + ); rcc.pll1divr.write(|w| unsafe { w.divn1().bits(100 - 1) // feebdack divider - .divp1().bits(2 - 1) // p output divider + .divp1().div2() // p output divider }); - rcc.cr.modify(|_, w| w.pll1on().set_bit()); - while rcc.cr.read().pll1rdy().bit_is_clear() {} + rcc.cr.modify(|_, w| w.pll1on().on()); + while !rcc.cr.read().pll1rdy().is_ready() {} // Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz rcc.pll2divr.write(|w| unsafe { @@ -140,24 +136,22 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { .divp1().bits(2 - 1) // p output divider .divq1().bits(2 - 1) // q output divider }); - rcc.cr.modify(|_, w| w.pll2on().set_bit()); - while rcc.cr.read().pll2rdy().bit_is_clear() {} + rcc.cr.modify(|_, w| w.pll2on().on()); + while !rcc.cr.read().pll2rdy().is_ready() {} // hclk 200 MHz, pclk 100 MHz - let dapb = 0b100; - rcc.d1cfgr.write(|w| unsafe { - w.d1cpre().bits(0) // sys_ck not divided - .hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2 - .d1ppre().bits(dapb) // rcc_pclk3 = rcc_hclk3 / 2 - }); - rcc.d2cfgr.write(|w| unsafe { - w.d2ppre1().bits(dapb) // rcc_pclk1 = rcc_hclk3 / 2 - .d2ppre2().bits(dapb) // rcc_pclk2 = rcc_hclk3 / 2 - - }); - rcc.d3cfgr.write(|w| unsafe { - w.d3ppre().bits(dapb) // rcc_pclk4 = rcc_hclk3 / 2 - }); + rcc.d1cfgr.write(|w| + w.d1cpre().div1() // sys_ck not divided + .hpre().div2() // rcc_hclk3 = sys_d1cpre_ck / 2 + .d1ppre().div2() // rcc_pclk3 = rcc_hclk3 / 2 + ); + rcc.d2cfgr.write(|w| + w.d2ppre1().div2() // rcc_pclk1 = rcc_hclk3 / 2 + .d2ppre2().div2() // rcc_pclk2 = rcc_hclk3 / 2 + ); + rcc.d3cfgr.write(|w| + w.d3ppre().div2() // rcc_pclk4 = rcc_hclk3 / 2 + ); // 2 wait states, 0b10 programming delay // 185-210 MHz @@ -168,24 +162,19 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { while flash.acr.read().latency().bits() != 2 {} // CSI for I/O compensationc ell - rcc.cr.modify(|_, w| w.csion().set_bit()); - while rcc.cr.read().csirdy().bit_is_clear() {} + rcc.cr.modify(|_, w| w.csion().on()); + while !rcc.cr.read().csirdy().is_ready() {} // Set system clock to pll1_p - rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p - while rcc.cfgr.read().sws().bits() != 0b011 {} + rcc.cfgr.modify(|_, w| w.sw().pll1()); + while !rcc.cfgr.read().sws().is_pll1() {} - rcc.d1ccipr.write(|w| unsafe { - w.ckpersrc().bits(1) // hse_ck - }); - rcc.d2ccip1r.modify(|_, w| unsafe { - w.spi123src().bits(1) // pll2_p - .spi45src().bits(1) // pll2_q - }); - - rcc.d3ccipr.modify(|_, w| unsafe { - w.spi6src().bits(1) // pll2_q - }); + rcc.d1ccipr.write(|w| w.ckpersel().hse()); + rcc.d2ccip1r.modify(|_, w| + w.spi123sel().pll2_p() + .spi45sel().pll2_q() + ); + rcc.d3ccipr.modify(|_, w| w.spi6sel().pll2_q()); } fn io_compensation_setup(syscfg: &stm32::SYSCFG) { From ef18eb38cae689bb36bd5968a72e35415234fe88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 6 May 2019 17:33:42 +0000 Subject: [PATCH 06/21] ethernet peripheral ownership, cs --- src/eth.rs | 464 ++++++++++++++++++++++++---------------------------- src/main.rs | 7 +- 2 files changed, 221 insertions(+), 250 deletions(-) diff --git a/src/eth.rs b/src/eth.rs index 4b12e4c..f95ebcf 100644 --- a/src/eth.rs +++ b/src/eth.rs @@ -1,5 +1,4 @@ use core::{slice, cmp}; -use cortex_m; use stm32h7::stm32h7x3 as stm32; use smoltcp::Result; use smoltcp::time::Instant; @@ -141,48 +140,40 @@ pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, const PHY_ADDR: u8 = 0; -fn phy_read(reg_addr: u8) -> u16 { - cortex_m::interrupt::free(|_cs| { - let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() }; - - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdioar.modify(|_, w| unsafe { - w - .pa().bits(PHY_ADDR) - .rda().bits(reg_addr) - .goc().bits(0b11) // read - .cr().bits(CLOCK_RANGE) - .mb().set_bit() - }); - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdiodr.read().md().bits() - }) +fn phy_read(reg_addr: u8, mac: &stm32::ETHERNET_MAC) -> u16 { + while mac.macmdioar.read().mb().bit_is_set() {} + mac.macmdioar.modify(|_, w| unsafe { + w + .pa().bits(PHY_ADDR) + .rda().bits(reg_addr) + .goc().bits(0b11) // read + .cr().bits(CLOCK_RANGE) + .mb().set_bit() + }); + while mac.macmdioar.read().mb().bit_is_set() {} + mac.macmdiodr.read().md().bits() } -fn phy_write(reg_addr: u8, reg_data: u16) { - cortex_m::interrupt::free(|_cs| { - let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() }; - - while mac.macmdioar.read().mb().bit_is_set() {} - mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); - mac.macmdioar.modify(|_, w| unsafe { - w - .pa().bits(PHY_ADDR) - .rda().bits(reg_addr) - .goc().bits(0b01) // write - .cr().bits(CLOCK_RANGE) - .mb().set_bit() - }); - while mac.macmdioar.read().mb().bit_is_set() {} - }) +fn phy_write(reg_addr: u8, reg_data: u16, mac: &stm32::ETHERNET_MAC) { + while mac.macmdioar.read().mb().bit_is_set() {} + mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); + mac.macmdioar.modify(|_, w| unsafe { + w + .pa().bits(PHY_ADDR) + .rda().bits(reg_addr) + .goc().bits(0b01) // write + .cr().bits(CLOCK_RANGE) + .mb().set_bit() + }); + while mac.macmdioar.read().mb().bit_is_set() {} } // Writes a value to an extended PHY register in MMD address space -fn phy_write_ext(reg_addr: u16, reg_data: u16) { - phy_write(PHY_REG_CTL, 0x0003); // set address - phy_write(PHY_REG_ADDAR, reg_addr); - phy_write(PHY_REG_CTL, 0x4003); // set data - phy_write(PHY_REG_ADDAR, reg_data); +fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &stm32::ETHERNET_MAC) { + phy_write(PHY_REG_CTL, 0x0003, mac); // set address + phy_write(PHY_REG_ADDAR, reg_addr, mac); + phy_write(PHY_REG_CTL, 0x4003, mac); // set data + phy_write(PHY_REG_ADDAR, reg_data, mac); } #[repr(align(4))] @@ -201,7 +192,7 @@ impl RxRing { } } - fn init(&mut self) { + unsafe fn init(&mut self, dma: &stm32::ETHERNET_DMA) { assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0); @@ -214,17 +205,10 @@ impl RxRing { } } - cortex_m::interrupt::free(|_cs| unsafe { - let dma = &*stm32::ETHERNET_DMA::ptr(); - - dma.dmacrx_dlar.write(|w| { - w.bits(&self.desc_buf as *const _ as u32) - }); - - dma.dmacrx_rlr.write(|w| { - w.rdrl().bits(self.desc_buf.len() as u16 - 1) - }); - }); + let addr = &self.desc_buf as *const _ as u32; + assert_eq!(addr & 0x3, 0); + dma.dmacrx_dlar.write(|w| w.bits(addr)); + dma.dmacrx_rlr.write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1)); self.cur_desc = 0; for _ in 0..self.desc_buf.len() { @@ -259,11 +243,10 @@ impl RxRing { self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP; self.desc_buf[self.cur_desc][3] = EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN; - let addr = &self.desc_buf[self.cur_desc] as *const _; - cortex_m::interrupt::free(|_cs| { - let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() }; - dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr as u32) }); - }); + let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; + assert_eq!(addr & 0x3, 0); + let dma = unsafe { stm32::Peripherals::steal().ETHERNET_DMA }; + dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) }); self.cur_desc = self.next_desc(); } @@ -285,7 +268,7 @@ impl TxRing { } } - fn init(&mut self) { + unsafe fn init(&mut self, dma: &stm32::ETHERNET_DMA) { assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0); @@ -299,21 +282,13 @@ impl TxRing { } self.cur_desc = 0; - cortex_m::interrupt::free(|_cs| unsafe { - let dma = &*stm32::ETHERNET_DMA::ptr(); - - dma.dmactx_dlar.write(|w| { - w.bits(&self.desc_buf as *const _ as u32) - }); - - dma.dmactx_rlr.write(|w| { - w.tdrl().bits(self.desc_buf.len() as u16 - 1) - }); - - dma.dmactx_dtpr.write(|w| { - w.bits(&self.desc_buf[0] as *const _ as u32) - }); - }); + let addr = &self.desc_buf as *const _ as u32; + assert_eq!(addr & 0x3, 0); + dma.dmactx_dlar.write(|w| w.bits(addr)); + dma.dmactx_rlr.write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1)); + let addr = &self.desc_buf[0] as *const _ as u32; + assert_eq!(addr & 0x3, 0); + dma.dmactx_dtpr.write(|w| w.bits(addr)); } fn next_desc(&self) -> usize { @@ -337,11 +312,10 @@ impl TxRing { self.desc_buf[self.cur_desc][3] = EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD; self.cur_desc = self.next_desc(); - let addr = &self.desc_buf[self.cur_desc] as *const _; - cortex_m::interrupt::free(|_cs| { - let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() }; - dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr as u32) }); - }); + let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; + assert_eq!(addr & 0x3, 0); + let dma = unsafe { stm32::Peripherals::steal().ETHERNET_DMA }; + dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) }); } } @@ -356,176 +330,174 @@ impl Device { } // After `init` is called, `Device` shall not be moved. - pub unsafe fn init(&mut self, mac: EthernetAddress) { - cortex_m::interrupt::free(|_cs| { - let eth_mac = &*stm32::ETHERNET_MAC::ptr(); - let eth_dma = &*stm32::ETHERNET_DMA::ptr(); - let eth_mtl = &*stm32::ETHERNET_MTL::ptr(); + pub unsafe fn init(&mut self, mac: EthernetAddress, + eth_mac: &stm32::ETHERNET_MAC, + eth_dma: &stm32::ETHERNET_DMA, + eth_mtl: &stm32::ETHERNET_MTL, + ) { + eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); + while eth_dma.dmamr.read().swr().bit_is_set() {} - eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); - while eth_dma.dmamr.read().swr().bit_is_set() {} + // 200 MHz + eth_mac.mac1ustcr.modify(|_, w| w.tic_1us_cntr().bits(200 - 1)); - // 200 MHz - eth_mac.mac1ustcr.modify(|_, w| w.tic_1us_cntr().bits(200 - 1)); - - // Configuration Register - eth_mac.maccr.modify(|_, w| { - w - .arpen().clear_bit() - .ipc().set_bit() - .ipg().bits(0b000) // 96 bit - .ecrsfd().clear_bit() - .dcrs().clear_bit() - .bl().bits(0b00) // 19 - .prelen().bits(0b00) // 7 - // CRC stripping for Type frames - .cst().set_bit() - // Fast Ethernet speed - .fes().set_bit() - // Duplex mode - .dm().set_bit() - // Automatic pad/CRC stripping - .acs().set_bit() - // Retry disable in half-duplex mode - .dr().set_bit() - }); - eth_mac.macecr.modify(|_, w| { - w - .eipgen().clear_bit() - .usp().clear_bit() - .spen().clear_bit() - .dcrcc().clear_bit() - }); - // Set the MAC address - eth_mac.maca0lr.write(|w| - w.addrlo().bits( u32::from(mac.0[0]) | - (u32::from(mac.0[1]) << 8) | - (u32::from(mac.0[2]) << 16) | - (u32::from(mac.0[3]) << 24)) - ); - eth_mac.maca0hr.write(|w| - w.addrhi().bits( u16::from(mac.0[4]) | - (u16::from(mac.0[5]) << 8)) - ); - // frame filter register - eth_mac.macpfr.modify(|_, w| { - w - .dntu().clear_bit() - .ipfe().clear_bit() - .vtfe().clear_bit() - .hpf().clear_bit() - .saf().clear_bit() - .saif().clear_bit() - .pcf().bits(0b00) - .dbf().clear_bit() - .pm().clear_bit() - .daif().clear_bit() - .hmc().clear_bit() - .huc().clear_bit() - // Receive All - .ra().clear_bit() - // Promiscuous mode - .pr().clear_bit() - }); - eth_mac.macwtr.write(|w| w.pwe().clear_bit()); - // Flow Control Register - eth_mac.macqtx_fcr.modify(|_, w| { - // Pause time - w.pt().bits(0x100) - }); - eth_mac.macrx_fcr.modify(|_, w| w); - eth_mtl.mtlrx_qomr.modify(|_, w| - w - // Receive store and forward - .rsf().set_bit() - // Dropping of TCP/IP checksum error frames disable - .dis_tcp_ef().clear_bit() - // Forward error frames - .fep().clear_bit() - // Forward undersized good packets - .fup().clear_bit() - ); - eth_mtl.mtltx_qomr.modify(|_, w| { - w - // Transmit store and forward - .tsf().set_bit() - }); - - if (phy_read(PHY_REG_ID1) != 0x0007) | (phy_read(PHY_REG_ID2) != 0xC131) { - error!("PHY ID error!"); - } - - phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET); - while phy_read(PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}; - phy_write_ext(PHY_REG_WUCSR, 0); - phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M); - /* - while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {}; - while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {}; - while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED) - != PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {}; - */ - - // operation mode register - eth_dma.dmamr.modify(|_, w| { - w - .intm().bits(0b00) - // Rx Tx priority ratio 1:1 - .pr().bits(0b000) - .txpr().clear_bit() - .da().clear_bit() - }); - // bus mode register - eth_dma.dmasbmr.modify(|_, w| { - // Address-aligned beats - w.aal().set_bit() - // Fixed burst - .fb().set_bit() - }); - eth_dma.dmaccr.modify(|_, w| { - w - .dsl().bits(0) - .pblx8().clear_bit() - .mss().bits(536) - }); - eth_dma.dmactx_cr.modify(|_, w| { - w - // Tx DMA PBL - .txpbl().bits(32) - .tse().clear_bit() - // Operate on second frame - .osf().clear_bit() - }); - - eth_dma.dmacrx_cr.modify(|_, w| { - w - // receive buffer size - .rbsz().bits(ETH_BUFFER_SIZE as u16) - // Rx DMA PBL - .rxpbl().bits(32) - // Disable flushing of received frames - .rpf().clear_bit() - }); - - self.rx.init(); - self.tx.init(); - - // Manage MAC transmission and reception - eth_mac.maccr.modify(|_, w| { - w.re().bit(true) // Receiver Enable - .te().bit(true) // Transmiter Enable - }); - eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit()); - - // Manage DMA transmission and reception - eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); - eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit()); - - eth_dma.dmacsr.modify(|_, w| - w.tps().set_bit() - .rps().set_bit() - ); + // Configuration Register + eth_mac.maccr.modify(|_, w| { + w + .arpen().clear_bit() + .ipc().set_bit() + .ipg().bits(0b000) // 96 bit + .ecrsfd().clear_bit() + .dcrs().clear_bit() + .bl().bits(0b00) // 19 + .prelen().bits(0b00) // 7 + // CRC stripping for Type frames + .cst().set_bit() + // Fast Ethernet speed + .fes().set_bit() + // Duplex mode + .dm().set_bit() + // Automatic pad/CRC stripping + .acs().set_bit() + // Retry disable in half-duplex mode + .dr().set_bit() }); + eth_mac.macecr.modify(|_, w| { + w + .eipgen().clear_bit() + .usp().clear_bit() + .spen().clear_bit() + .dcrcc().clear_bit() + }); + // Set the MAC address + eth_mac.maca0lr.write(|w| + w.addrlo().bits( u32::from(mac.0[0]) | + (u32::from(mac.0[1]) << 8) | + (u32::from(mac.0[2]) << 16) | + (u32::from(mac.0[3]) << 24)) + ); + eth_mac.maca0hr.write(|w| + w.addrhi().bits( u16::from(mac.0[4]) | + (u16::from(mac.0[5]) << 8)) + ); + // frame filter register + eth_mac.macpfr.modify(|_, w| { + w + .dntu().clear_bit() + .ipfe().clear_bit() + .vtfe().clear_bit() + .hpf().clear_bit() + .saf().clear_bit() + .saif().clear_bit() + .pcf().bits(0b00) + .dbf().clear_bit() + .pm().clear_bit() + .daif().clear_bit() + .hmc().clear_bit() + .huc().clear_bit() + // Receive All + .ra().clear_bit() + // Promiscuous mode + .pr().clear_bit() + }); + eth_mac.macwtr.write(|w| w.pwe().clear_bit()); + // Flow Control Register + eth_mac.macqtx_fcr.modify(|_, w| { + // Pause time + w.pt().bits(0x100) + }); + eth_mac.macrx_fcr.modify(|_, w| w); + eth_mtl.mtlrx_qomr.modify(|_, w| + w + // Receive store and forward + .rsf().set_bit() + // Dropping of TCP/IP checksum error frames disable + .dis_tcp_ef().clear_bit() + // Forward error frames + .fep().clear_bit() + // Forward undersized good packets + .fup().clear_bit() + ); + eth_mtl.mtltx_qomr.modify(|_, w| { + w + // Transmit store and forward + .tsf().set_bit() + }); + + if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007) | (phy_read(PHY_REG_ID2, eth_mac) != 0xC131) { + error!("PHY ID error!"); + } + + phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac); + while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}; + phy_write_ext(PHY_REG_WUCSR, 0, eth_mac); + phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M, eth_mac); + /* + while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {}; + while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {}; + while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED) + != PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {}; + */ + + // operation mode register + eth_dma.dmamr.modify(|_, w| { + w + .intm().bits(0b00) + // Rx Tx priority ratio 1:1 + .pr().bits(0b000) + .txpr().clear_bit() + .da().clear_bit() + }); + // bus mode register + eth_dma.dmasbmr.modify(|_, w| { + // Address-aligned beats + w.aal().set_bit() + // Fixed burst + .fb().set_bit() + }); + eth_dma.dmaccr.modify(|_, w| { + w + .dsl().bits(0) + .pblx8().clear_bit() + .mss().bits(536) + }); + eth_dma.dmactx_cr.modify(|_, w| { + w + // Tx DMA PBL + .txpbl().bits(32) + .tse().clear_bit() + // Operate on second frame + .osf().clear_bit() + }); + + eth_dma.dmacrx_cr.modify(|_, w| { + w + // receive buffer size + .rbsz().bits(ETH_BUFFER_SIZE as u16) + // Rx DMA PBL + .rxpbl().bits(32) + // Disable flushing of received frames + .rpf().clear_bit() + }); + + self.rx.init(eth_dma); + self.tx.init(eth_dma); + + // Manage MAC transmission and reception + eth_mac.maccr.modify(|_, w| { + w.re().bit(true) // Receiver Enable + .te().bit(true) // Transmiter Enable + }); + eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit()); + + // Manage DMA transmission and reception + eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit()); + eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit()); + + eth_dma.dmacsr.modify(|_, w| + w.tps().set_bit() + .rps().set_bit() + ); } } @@ -586,8 +558,7 @@ impl<'a> phy::TxToken for TxToken<'a> { } } -pub unsafe fn interrupt_handler() { - let eth_dma = &*stm32::ETHERNET_DMA::ptr(); +pub unsafe fn interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) { eth_dma.dmacsr.write(|w| w .nis().set_bit() @@ -596,8 +567,7 @@ pub unsafe fn interrupt_handler() { ); } -pub unsafe fn enable_interrupt() { - let eth_dma = &*stm32::ETHERNET_DMA::ptr(); +pub unsafe fn enable_interrupt(eth_dma: &stm32::ETHERNET_DMA) { eth_dma.dmacier.modify(|_, w| w .nie().set_bit() diff --git a/src/main.rs b/src/main.rs index 3ea48d9..8ffc57f 100644 --- a/src/main.rs +++ b/src/main.rs @@ -612,7 +612,7 @@ fn main() -> ! { let device = unsafe { &mut ETHERNET }; let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); - unsafe { device.init(hardware_addr) }; + unsafe { device.init(hardware_addr, &dp.ETHERNET_MAC, &dp.ETHERNET_DMA, &dp.ETHERNET_MTL) }; let mut neighbor_cache_storage = [None; 8]; let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); @@ -626,7 +626,7 @@ fn main() -> ! { let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); - unsafe { eth::enable_interrupt(); } + unsafe { eth::enable_interrupt(&dp.ETHERNET_DMA); } unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio cp.NVIC.enable(stm32::Interrupt::ETH); @@ -715,8 +715,9 @@ fn SPI1() { #[interrupt] fn ETH() { + let dma = unsafe { &stm32::Peripherals::steal().ETHERNET_DMA }; ETHERNET_PENDING.store(true, Ordering::Relaxed); - unsafe { eth::interrupt_handler() } + unsafe { eth::interrupt_handler(dma) } } #[exception] From 7501ea1963a7d642e273f78602c5e42bc270976c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 30 May 2019 16:03:48 +0000 Subject: [PATCH 07/21] use rtfm [wip] --- Cargo.lock | 62 +++++++++ Cargo.toml | 4 + src/main.rs | 389 +++++++++++++++++++++++++++------------------------- 3 files changed, 271 insertions(+), 184 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 45c07a7..20e28b8 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1,5 +1,10 @@ # This file is automatically @generated by Cargo. # It is not intended for manual editing. +[[package]] +name = "aligned" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" + [[package]] name = "aligned" version = "0.3.1" @@ -40,6 +45,17 @@ name = "cfg-if" version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" +[[package]] +name = "cortex-m" +version = "0.5.10" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "aligned 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", + "bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", + "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "cortex-m" version = "0.6.0" @@ -80,6 +96,27 @@ dependencies = [ "syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)", ] +[[package]] +name = "cortex-m-rtfm" +version = "0.5.0-alpha.1" +source = "git+https://github.com/japaric/cortex-m-rtfm#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" +dependencies = [ + "cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm)", + "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", +] + +[[package]] +name = "cortex-m-rtfm-macros" +version = "0.5.0-alpha.1" +source = "git+https://github.com/japaric/cortex-m-rtfm#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" +dependencies = [ + "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "cortex-m-semihosting" version = "0.3.3" @@ -104,6 +141,14 @@ dependencies = [ "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", ] +[[package]] +name = "generic-array" +version = "0.13.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "hash32" version = "0.1.0" @@ -122,6 +167,16 @@ dependencies = [ "hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", ] +[[package]] +name = "heapless" +version = "0.5.0-alpha.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +dependencies = [ + "as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", + "generic-array 0.13.0 (registry+https://github.com/rust-lang/crates.io-index)", + "hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", +] + [[package]] name = "log" version = "0.4.6" @@ -256,6 +311,7 @@ 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"fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6" "checksum panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "2c14a66511ed17b6a8b4256b868d7fd207836d891db15eea5195dbcaf87e630f" diff --git a/Cargo.toml b/Cargo.toml index d43c75b..10adbb4 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -53,6 +53,10 @@ version = "0.5" features = ["proto-ipv4", "socket-tcp"] default-features = false +[dependencies.cortex-m-rtfm] +git = "https://github.com/japaric/cortex-m-rtfm" +features = ["timer-queue"] + [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] bkpt = [ ] diff --git a/src/main.rs b/src/main.rs index 14b08ec..9ef8579 100644 --- a/src/main.rs +++ b/src/main.rs @@ -13,12 +13,10 @@ extern crate panic_semihosting; extern crate log; use core::ptr; -use core::cell::RefCell; use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; use core::fmt::Write; -use cortex_m_rt::{entry, exception}; -use stm32h7::stm32h7x3::{self as stm32, Peripherals, CorePeripherals, interrupt}; -use cortex_m::interrupt::Mutex; +use cortex_m_rt::{exception}; +use stm32h7::stm32h7x3::{self as stm32, interrupt}; use heapless::{String, Vec, consts::*}; use smoltcp as net; @@ -37,7 +35,7 @@ fn init_log() {} #[cfg(feature = "semihosting")] fn init_log() { use log::LevelFilter; - use cortex_m_log::log::{Logger, init}; + use cortex_m_log::log::{Logger, init as init_log}; use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout}; static mut LOGGER: Option>> = None; let logger = Logger { @@ -48,7 +46,7 @@ fn init_log() { LOGGER.get_or_insert(logger) }; - init(logger).unwrap(); + init_log(logger).unwrap(); } // Pull in build information (from `built` crate) @@ -492,8 +490,7 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz dma1.st[1].cr.modify(|_, w| w.en().set_bit()); } -type SpiPs = Option<(stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>; -static SPIP: Mutex> = Mutex::new(RefCell::new(None)); +const SCALE: f32 = ((1 << 15) - 1) as f32; #[link_section = ".sram1.datspi"] static mut DAT: u32 = 0x201; // EN | CSTART @@ -518,153 +515,231 @@ macro_rules! create_socket { ) } +#[rtfm::app(device = stm32h7::stm32h7x3)] +const APP: () = { + static SPI: (stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5) = (); -#[entry] -fn main() -> ! { - let mut cp = CorePeripherals::take().unwrap(); - let dp = Peripherals::take().unwrap(); + static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2]; + static mut IIR_CH: [IIR; 2] = [ + IIR { + ba: [0., 0., 0., 0., 0.], + y_offset: 0., + y_min: -SCALE - 1., + y_max: SCALE + }; + 2]; + // static IFACE: net::iface::EthernetInterface<'static, 'static, 'static, eth::Device> = (); + // static SOCKETS: net::socket::SocketSet<'static, 'static, 'static> = (); - let rcc = dp.RCC; - rcc_reset(&rcc); + #[init] + fn init(c: init::Context) -> init::LateResources { + let dp = c.device; + let cp = c.core; - init_log(); - // info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap()); - // info!("Built on {}", build_info::BUILT_TIME_UTC); - // info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET); + let rcc = dp.RCC; + rcc_reset(&rcc); - pwr_setup(&dp.PWR); - rcc_pll_setup(&rcc, &dp.FLASH); - rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); - io_compensation_setup(&dp.SYSCFG); + init_log(); + // info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap()); + // info!("Built on {}", build_info::BUILT_TIME_UTC); + // info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET); - // 100 MHz - cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core); - cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10); - cp.SYST.enable_counter(); - cp.SYST.enable_interrupt(); - unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority + pwr_setup(&dp.PWR); + rcc_pll_setup(&rcc, &dp.FLASH); + rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); + io_compensation_setup(&dp.SYSCFG); - cp.SCB.enable_icache(); - // TODO: ETH DMA coherence issues - // cp.SCB.enable_dcache(&mut cp.CPUID); - cp.DWT.enable_cycle_counter(); + // 100 MHz +/* + cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core); + cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10); + cp.SYST.enable_counter(); + cp.SYST.enable_interrupt(); + unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority +*/ - rcc.ahb4enr.modify(|_, w| - w.gpioaen().set_bit() - .gpioben().set_bit() - .gpiocen().set_bit() - .gpioden().set_bit() - .gpioeen().set_bit() - .gpiofen().set_bit() - .gpiogen().set_bit() - ); - gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOF, &dp.GPIOG); + cp.SCB.enable_icache(); + // TODO: ETH DMA coherence issues + // cp.SCB.enable_dcache(&mut cp.CPUID); + // cp.DWT.enable_cycle_counter(); - rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit()); - let spi2 = dp.SPI2; - spi2_setup(&spi2); + rcc.ahb4enr.modify(|_, w| + w.gpioaen().set_bit() + .gpioben().set_bit() + .gpiocen().set_bit() + .gpioden().set_bit() + .gpioeen().set_bit() + .gpiofen().set_bit() + .gpiogen().set_bit() + ); + gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOF, &dp.GPIOG); - rcc.apb2enr.modify(|_, w| w.spi4en().set_bit()); - let spi4 = dp.SPI4; - spi4_setup(&spi4); + rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit()); + let spi2 = dp.SPI2; + spi2_setup(&spi2); - rcc.apb2enr.modify(|_, w| w.spi1en().set_bit()); - let spi1 = dp.SPI1; - spi1_setup(&spi1); - spi1.ier.write(|w| w.eotie().set_bit()); + rcc.apb2enr.modify(|_, w| w.spi4en().set_bit()); + let spi4 = dp.SPI4; + spi4_setup(&spi4); - rcc.apb2enr.modify(|_, w| w.spi5en().set_bit()); - let spi5 = dp.SPI5; - spi5_setup(&spi5); - // spi5.ier.write(|w| w.eotie().set_bit()); + rcc.apb2enr.modify(|_, w| w.spi1en().set_bit()); + let spi1 = dp.SPI1; + spi1_setup(&spi1); + spi1.ier.write(|w| w.eotie().set_bit()); - rcc.ahb2enr.modify(|_, w| - w - .sram1en().set_bit() - .sram2en().set_bit() - .sram3en().set_bit() - ); - rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit()); - // init SRAM1 rodata can't load with sram1 disabled - unsafe { DAT = 0x201 }; // EN | CSTART - cortex_m::asm::dsb(); - let dat_addr = unsafe { &DAT as *const _ } as usize; - cp.SCB.clean_dcache_by_address(dat_addr, 4); + rcc.apb2enr.modify(|_, w| w.spi5en().set_bit()); + let spi5 = dp.SPI5; + spi5_setup(&spi5); + // spi5.ier.write(|w| w.eotie().set_bit()); - dma1_setup(&dp.DMA1, &dp.DMAMUX1, dat_addr, - &spi1.cr1 as *const _ as usize, - &spi5.cr1 as *const _ as usize); + rcc.ahb2enr.modify(|_, w| + w + .sram1en().set_bit() + .sram2en().set_bit() + .sram3en().set_bit() + ); + rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit()); + // init SRAM1 rodata can't load with sram1 disabled + unsafe { DAT = 0x201 }; // EN | CSTART + cortex_m::asm::dsb(); + let dat_addr = unsafe { &DAT as *const _ } as usize; + cp.SCB.clean_dcache_by_address(dat_addr, 4); - rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); + dma1_setup(&dp.DMA1, &dp.DMAMUX1, dat_addr, + &spi1.cr1 as *const _ as usize, + &spi5.cr1 as *const _ as usize); - // work around the SPI stall erratum - let dbgmcu = dp.DBGMCU; - dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit()); + rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit()); - eth::setup(&rcc, &dp.SYSCFG); - eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); + // work around the SPI stall erratum + let dbgmcu = dp.DBGMCU; + dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit()); - let device = unsafe { &mut ETHERNET }; - let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); - unsafe { device.init(hardware_addr, &dp.ETHERNET_MAC, &dp.ETHERNET_DMA, &dp.ETHERNET_MTL) }; - let mut neighbor_cache_storage = [None; 8]; - let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); - let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); - let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)]; - let mut iface = net::iface::EthernetInterfaceBuilder::new(device) - .ethernet_addr(hardware_addr) - .neighbor_cache(neighbor_cache) - .ip_addrs(&mut ip_addrs[..]) - .finalize(); - let mut socket_set_entries: [_; 8] = Default::default(); - let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); - create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); - create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); + eth::setup(&rcc, &dp.SYSCFG); + eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); - unsafe { eth::enable_interrupt(&dp.ETHERNET_DMA); } - unsafe { cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); } // mid prio - cp.NVIC.enable(stm32::Interrupt::ETH); + let device = unsafe { &mut ETHERNET }; + let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); + unsafe { device.init(hardware_addr, &dp.ETHERNET_MAC, &dp.ETHERNET_DMA, &dp.ETHERNET_MTL) }; + let mut neighbor_cache_storage = [None; 8]; + let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); + let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); + let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)]; + let mut iface = net::iface::EthernetInterfaceBuilder::new(device) + .ethernet_addr(hardware_addr) + .neighbor_cache(neighbor_cache) + .ip_addrs(&mut ip_addrs[..]) + .finalize(); + let mut socket_set_entries: [_; 8] = Default::default(); + let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]); + create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); + create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); - tim2_setup(&dp.TIM2); + unsafe { eth::enable_interrupt(&dp.ETHERNET_DMA); } - unsafe { cp.NVIC.set_priority(stm32::Interrupt::SPI1, 0); } // highest prio - cortex_m::interrupt::free(|cs| { - cp.NVIC.enable(stm32::Interrupt::SPI1); - SPIP.borrow(cs).replace(Some((spi1, spi2, spi4, spi5))); - }); + tim2_setup(&dp.TIM2); - let mut last = 0; - let mut server = Server::new(); - loop { - // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } - let time = TIME.load(Ordering::Relaxed); - { - let socket = &mut *sockets.get::(tcp_handle0); - if !(socket.is_open() || socket.is_listening()) { - socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else if last != time && socket.can_send() { - last = time; - handle_status(socket, time); - } - } - { - let socket = &mut *sockets.get::(tcp_handle1); - if !(socket.is_open() || socket.is_listening()) { - socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else { - server.handle_command(socket); - } + init::LateResources { + SPI: (spi1, spi2, spi4, spi5), + // IFACE: iface, + // SOCKETS: sockets, } + } - if !match iface.poll(&mut sockets, net::time::Instant::from_millis(time as i64)) { - Ok(changed) => changed, - Err(net::Error::Unrecognized) => true, - Err(e) => { info!("iface poll error: {:?}", e); true } - } { + #[idle] + fn idle(_: idle::Context) -> ! { + loop { cortex_m::asm::wfi(); } } -} + + // seems to slow it down + // #[link_section = ".data.spi1"] + #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 1)] + fn SPI1(c: SPI1::Context) { + #[cfg(feature = "bkpt")] + cortex_m::asm::bkpt(); + let (spi1, spi2, spi4, spi5) = c.resources.SPI; + let iir_ch = c.resources.IIR_CH; + let iir_state = c.resources.IIR_STATE; + + let sr = spi1.sr.read(); + if sr.eot().bit_is_set() { + spi1.ifcr.write(|w| w.eotc().set_bit()); + } + if sr.rxp().bit_is_set() { + let rxdr = &spi1.rxdr as *const _ as *const u16; + let a = unsafe { ptr::read_volatile(rxdr) }; + let x0 = f32::from(a as i16); + let y0 = unsafe { iir_ch[0].update(&mut iir_state[0], x0) }; + let d = y0 as i16 as u16 ^ 0x8000; + let txdr = &spi2.txdr as *const _ as *mut u16; + unsafe { ptr::write_volatile(txdr, d) }; + } + + let sr = spi5.sr.read(); + if sr.eot().bit_is_set() { + spi5.ifcr.write(|w| w.eotc().set_bit()); + } + if sr.rxp().bit_is_set() { + let rxdr = &spi5.rxdr as *const _ as *const u16; + let a = unsafe { ptr::read_volatile(rxdr) }; + let x0 = f32::from(a as i16); + let y0 = unsafe { iir_ch[1].update(&mut iir_state[1], x0) }; + let d = y0 as i16 as u16 ^ 0x8000; + let txdr = &spi4.txdr as *const _ as *mut u16; + unsafe { ptr::write_volatile(txdr, d) }; + } + #[cfg(feature = "bkpt")] + cortex_m::asm::bkpt(); + } + + #[interrupt(resources = [], priority = 7)] + fn ETH(_: ETH::Context) { + let dma = unsafe { &stm32::Peripherals::steal().ETHERNET_DMA }; + ETHERNET_PENDING.store(true, Ordering::Relaxed); + unsafe { eth::interrupt_handler(dma) } + } + + extern "C" { + fn DCMI(); + fn JPEG(); + fn SDMMC(); + } +}; + +/* + let mut last = 0; + let mut server = Server::new(); + loop { + // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } + let time = TIME.load(Ordering::Relaxed); + { + let socket = &mut *sockets.get::(tcp_handle0); + if !(socket.is_open() || socket.is_listening()) { + socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); + } else if last != time && socket.can_send() { + last = time; + handle_status(socket, time); + } + } + { + let socket = &mut *sockets.get::(tcp_handle1); + if !(socket.is_open() || socket.is_listening()) { + socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); + } else { + server.handle_command(socket); + } + } + + if !match iface.poll(&mut sockets, net::time::Instant::from_millis(time as i64)) { + Ok(changed) => changed, + Err(net::Error::Unrecognized) => true, + Err(e) => { info!("iface poll error: {:?}", e); true } + } { + cortex_m::asm::wfi(); + } + } #[derive(Deserialize,Serialize)] struct Request { @@ -760,65 +835,11 @@ struct Status { y1: f32 } -const SCALE: f32 = ((1 << 15) - 1) as f32; -static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2]; -static mut IIR_CH: [IIR; 2] = [ - IIR{ ba: [0., 0., 0., 0., 0.], y_offset: 0., - y_min: -SCALE - 1., y_max: SCALE }; 2]; - -// seems to slow it down -// #[link_section = ".data.spi1"] -#[interrupt] -fn SPI1() { - #[cfg(feature = "bkpt")] - cortex_m::asm::bkpt(); - cortex_m::interrupt::free(|cs| { - let spip = SPIP.borrow(cs).borrow(); - let (spi1, spi2, spi4, spi5) = spip.as_ref().unwrap(); - - let sr = spi1.sr.read(); - if sr.eot().bit_is_set() { - spi1.ifcr.write(|w| w.eotc().set_bit()); - } - if sr.rxp().bit_is_set() { - let rxdr = &spi1.rxdr as *const _ as *const u16; - let a = unsafe { ptr::read_volatile(rxdr) }; - let x0 = f32::from(a as i16); - let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) }; - let d = y0 as i16 as u16 ^ 0x8000; - let txdr = &spi2.txdr as *const _ as *mut u16; - unsafe { ptr::write_volatile(txdr, d) }; - } - - let sr = spi5.sr.read(); - if sr.eot().bit_is_set() { - spi5.ifcr.write(|w| w.eotc().set_bit()); - } - if sr.rxp().bit_is_set() { - let rxdr = &spi5.rxdr as *const _ as *const u16; - let a = unsafe { ptr::read_volatile(rxdr) }; - let x0 = f32::from(a as i16); - let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) }; - let d = y0 as i16 as u16 ^ 0x8000; - let txdr = &spi4.txdr as *const _ as *mut u16; - unsafe { ptr::write_volatile(txdr, d) }; - } - }); - #[cfg(feature = "bkpt")] - cortex_m::asm::bkpt(); -} - -#[interrupt] -fn ETH() { - let dma = unsafe { &stm32::Peripherals::steal().ETHERNET_DMA }; - ETHERNET_PENDING.store(true, Ordering::Relaxed); - unsafe { eth::interrupt_handler(dma) } -} - #[exception] fn SysTick() { TIME.fetch_add(1, Ordering::Relaxed); } +*/ #[exception] fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { From 6be0ccfc6ab21d1b0ea7dbd57e9bbe71a8a37b42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 30 May 2019 16:18:59 +0000 Subject: [PATCH 08/21] rtfm: continue work --- src/main.rs | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/src/main.rs b/src/main.rs index 9ef8579..3d158ff 100644 --- a/src/main.rs +++ b/src/main.rs @@ -495,7 +495,6 @@ const SCALE: f32 = ((1 << 15) - 1) as f32; #[link_section = ".sram1.datspi"] static mut DAT: u32 = 0x201; // EN | CSTART -static TIME: AtomicU32 = AtomicU32::new(0); static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); #[link_section = ".sram3.eth"] @@ -531,7 +530,7 @@ const APP: () = { // static IFACE: net::iface::EthernetInterface<'static, 'static, 'static, eth::Device> = (); // static SOCKETS: net::socket::SocketSet<'static, 'static, 'static> = (); - #[init] + #[init(schedule = [tick])] fn init(c: init::Context) -> init::LateResources { let dp = c.device; let cp = c.core; @@ -549,15 +548,6 @@ const APP: () = { rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); io_compensation_setup(&dp.SYSCFG); - // 100 MHz -/* - cp.SYST.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core); - cp.SYST.set_reload(cortex_m::peripheral::SYST::get_ticks_per_10ms()*200/10); - cp.SYST.enable_counter(); - cp.SYST.enable_interrupt(); - unsafe { cp.SCB.shpr[11].write(128); } // systick exception priority -*/ - cp.SCB.enable_icache(); // TODO: ETH DMA coherence issues // cp.SCB.enable_dcache(&mut cp.CPUID); @@ -639,6 +629,8 @@ const APP: () = { tim2_setup(&dp.TIM2); + c.schedule.tick(rtfm::Instant::now()).unwrap(); + init::LateResources { SPI: (spi1, spi2, spi4, spi5), // IFACE: iface, @@ -653,6 +645,13 @@ const APP: () = { } } + #[task(schedule = [tick])] + fn tick(c: tick::Context) { + // let now = rtfm::Instant::now(); + const PERIOD: u32 = 200_000_000; + c.schedule.tick(c.scheduled + PERIOD.cycles()).unwrap(); + } + // seems to slow it down // #[link_section = ".data.spi1"] #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 1)] @@ -671,7 +670,7 @@ const APP: () = { let rxdr = &spi1.rxdr as *const _ as *const u16; let a = unsafe { ptr::read_volatile(rxdr) }; let x0 = f32::from(a as i16); - let y0 = unsafe { iir_ch[0].update(&mut iir_state[0], x0) }; + let y0 = iir_ch[0].update(&mut iir_state[0], x0); let d = y0 as i16 as u16 ^ 0x8000; let txdr = &spi2.txdr as *const _ as *mut u16; unsafe { ptr::write_volatile(txdr, d) }; @@ -685,7 +684,7 @@ const APP: () = { let rxdr = &spi5.rxdr as *const _ as *const u16; let a = unsafe { ptr::read_volatile(rxdr) }; let x0 = f32::from(a as i16); - let y0 = unsafe { iir_ch[1].update(&mut iir_state[1], x0) }; + let y0 = iir_ch[1].update(&mut iir_state[1], x0); let d = y0 as i16 as u16 ^ 0x8000; let txdr = &spi4.txdr as *const _ as *mut u16; unsafe { ptr::write_volatile(txdr, d) }; @@ -702,6 +701,7 @@ const APP: () = { } extern "C" { + // hw interrupt handlers for RTFM to use for scheduling tasks, one per priority fn DCMI(); fn JPEG(); fn SDMMC(); @@ -834,11 +834,6 @@ struct Status { x1: f32, y1: f32 } - -#[exception] -fn SysTick() { - TIME.fetch_add(1, Ordering::Relaxed); -} */ #[exception] From b646c44c1cc1b381e408cb87e39660c3a959b49c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 30 May 2019 20:57:41 +0000 Subject: [PATCH 09/21] rtfm: move ethernet into idle --- src/main.rs | 174 ++++++++++++++++++++++++++-------------------------- 1 file changed, 87 insertions(+), 87 deletions(-) diff --git a/src/main.rs b/src/main.rs index 3d158ff..dc7419b 100644 --- a/src/main.rs +++ b/src/main.rs @@ -497,9 +497,6 @@ static mut DAT: u32 = 0x201; // EN | CSTART static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); -#[link_section = ".sram3.eth"] -static mut ETHERNET: eth::Device = eth::Device::new(); - const TCP_RX_BUFFER_SIZE: usize = 8192; const TCP_TX_BUFFER_SIZE: usize = 8192; @@ -527,8 +524,10 @@ const APP: () = { y_max: SCALE }; 2]; - // static IFACE: net::iface::EthernetInterface<'static, 'static, 'static, eth::Device> = (); - // static SOCKETS: net::socket::SocketSet<'static, 'static, 'static> = (); + static ETHERNET_PERIPH: (stm32::ETHERNET_MAC, stm32::ETHERNET_DMA, stm32::ETHERNET_MTL) = (); + + #[link_section = ".sram3.eth"] + static mut ETHERNET: eth::Device = eth::Device::new(); #[init(schedule = [tick])] fn init(c: init::Context) -> init::LateResources { @@ -605,17 +604,30 @@ const APP: () = { let dbgmcu = dp.DBGMCU; dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit()); + tim2_setup(&dp.TIM2); + eth::setup(&rcc, &dp.SYSCFG); eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); - let device = unsafe { &mut ETHERNET }; + c.schedule.tick(rtfm::Instant::now()).unwrap(); + + init::LateResources { + SPI: (spi1, spi2, spi4, spi5), + ETHERNET_PERIPH: (dp.ETHERNET_MAC, dp.ETHERNET_DMA, dp.ETHERNET_MTL), + } + } + + #[idle(resources = [ETHERNET, ETHERNET_PERIPH])] + fn idle(c: idle::Context) -> ! { + let (MAC, DMA, MTL) = c.resources.ETHERNET_PERIPH; + let hardware_addr = net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]); - unsafe { device.init(hardware_addr, &dp.ETHERNET_MAC, &dp.ETHERNET_DMA, &dp.ETHERNET_MTL) }; + unsafe { c.resources.ETHERNET.init(hardware_addr, MAC, DMA, MTL) }; let mut neighbor_cache_storage = [None; 8]; let neighbor_cache = net::iface::NeighborCache::new(&mut neighbor_cache_storage[..]); let local_addr = net::wire::IpAddress::v4(10, 0, 16, 99); let mut ip_addrs = [net::wire::IpCidr::new(local_addr, 24)]; - let mut iface = net::iface::EthernetInterfaceBuilder::new(device) + let mut iface = net::iface::EthernetInterfaceBuilder::new(c.resources.ETHERNET) .ethernet_addr(hardware_addr) .neighbor_cache(neighbor_cache) .ip_addrs(&mut ip_addrs[..]) @@ -625,36 +637,56 @@ const APP: () = { create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0); create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); - unsafe { eth::enable_interrupt(&dp.ETHERNET_DMA); } - - tim2_setup(&dp.TIM2); - - c.schedule.tick(rtfm::Instant::now()).unwrap(); - - init::LateResources { - SPI: (spi1, spi2, spi4, spi5), - // IFACE: iface, - // SOCKETS: sockets, - } - } - - #[idle] - fn idle(_: idle::Context) -> ! { + // unsafe { eth::enable_interrupt(DMA); } + let mut last = 0u32; + let mut last_iter = rtfm::Instant::now(); + //let mut server = Server::new(); loop { - cortex_m::asm::wfi(); + // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } + let mut time = last; + if rtfm::Instant::now() >= last_iter + 200_000.cycles() { + last_iter += 200_000.cycles(); + time += 1; + } + { + let socket = &mut *sockets.get::(tcp_handle0); + if !(socket.is_open() || socket.is_listening()) { + socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); + } else if time > last && socket.can_send() { + last = time; + //handle_status(socket, time); + } + } + { + let socket = &mut *sockets.get::(tcp_handle1); + if !(socket.is_open() || socket.is_listening()) { + socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); + } else { + //server.handle_command(socket); + } + } + + if !match iface.poll(&mut sockets, net::time::Instant::from_millis(time as i64)) { + Ok(changed) => changed, + Err(net::Error::Unrecognized) => true, + Err(e) => { info!("iface poll error: {:?}", e); true } + } { + // cortex_m::asm::wfi(); + } } } #[task(schedule = [tick])] fn tick(c: tick::Context) { - // let now = rtfm::Instant::now(); + static mut TIME: u32 = 0; + *TIME += 1; const PERIOD: u32 = 200_000_000; c.schedule.tick(c.scheduled + PERIOD.cycles()).unwrap(); } // seems to slow it down // #[link_section = ".data.spi1"] - #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 1)] + #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 3)] fn SPI1(c: SPI1::Context) { #[cfg(feature = "bkpt")] cortex_m::asm::bkpt(); @@ -664,7 +696,7 @@ const APP: () = { let sr = spi1.sr.read(); if sr.eot().bit_is_set() { - spi1.ifcr.write(|w| w.eotc().set_bit()); + spi1.ifcr.write(|w| w.eotc().set_bit()); } if sr.rxp().bit_is_set() { let rxdr = &spi1.rxdr as *const _ as *const u16; @@ -678,7 +710,7 @@ const APP: () = { let sr = spi5.sr.read(); if sr.eot().bit_is_set() { - spi5.ifcr.write(|w| w.eotc().set_bit()); + spi5.ifcr.write(|w| w.eotc().set_bit()); } if sr.rxp().bit_is_set() { let rxdr = &spi5.rxdr as *const _ as *const u16; @@ -693,54 +725,24 @@ const APP: () = { cortex_m::asm::bkpt(); } - #[interrupt(resources = [], priority = 7)] - fn ETH(_: ETH::Context) { - let dma = unsafe { &stm32::Peripherals::steal().ETHERNET_DMA }; + /* + #[interrupt(resources = [ETHERNET_PERIPH], priority = 1)] + fn ETH(c: ETH::Context) { + let dma = &c.resources.ETHERNET_PERIPH.1; ETHERNET_PENDING.store(true, Ordering::Relaxed); unsafe { eth::interrupt_handler(dma) } } + */ extern "C" { - // hw interrupt handlers for RTFM to use for scheduling tasks, one per priority + // hw interrupt handlers for RTFM to use for scheduling tasks + // one per priority fn DCMI(); fn JPEG(); fn SDMMC(); } }; -/* - let mut last = 0; - let mut server = Server::new(); - loop { - // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } - let time = TIME.load(Ordering::Relaxed); - { - let socket = &mut *sockets.get::(tcp_handle0); - if !(socket.is_open() || socket.is_listening()) { - socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else if last != time && socket.can_send() { - last = time; - handle_status(socket, time); - } - } - { - let socket = &mut *sockets.get::(tcp_handle1); - if !(socket.is_open() || socket.is_listening()) { - socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else { - server.handle_command(socket); - } - } - - if !match iface.poll(&mut sockets, net::time::Instant::from_millis(time as i64)) { - Ok(changed) => changed, - Err(net::Error::Unrecognized) => true, - Err(e) => { info!("iface poll error: {:?}", e); true } - } { - cortex_m::asm::wfi(); - } - } - #[derive(Deserialize,Serialize)] struct Request { channel: u8, @@ -753,10 +755,13 @@ struct Response<'a> { message: &'a str, } -fn reply(socket: &mut net::socket::TcpSocket, msg: &T) { - let mut u: String = to_string(msg).unwrap(); - u.push('\n').unwrap(); - socket.write_str(&u).unwrap(); +#[derive(Serialize)] +struct Status { + t: u32, + x0: f32, + y0: f32, + x1: f32, + y1: f32 } struct Server { @@ -764,6 +769,12 @@ struct Server { discard: bool, } +fn reply(socket: &mut net::socket::TcpSocket, msg: &T) { + let mut u: String = to_string(msg).unwrap(); + u.push('\n').unwrap(); + socket.write_str(&u).unwrap(); +} + impl Server { fn new() -> Self { Self { data: Vec::new(), discard: false } @@ -796,9 +807,7 @@ impl Server { if request.channel > 1 { Response{ code: 530, message: "invalid channel" } } else { - cortex_m::interrupt::free(|_| { - unsafe { IIR_CH[request.channel as usize] = request.iir; }; - }); + //unsafe { IIR_CH[request.channel as usize] = request.iir; }; Response{ code: 200, message: "ok" } } }, @@ -815,27 +824,18 @@ impl Server { } } -fn handle_status(socket: &mut net::socket::TcpSocket, time: u32) { +fn handle_status(socket: &mut net::socket::TcpSocket, time: u32, + iir_state: &[IIRState]) { let s = unsafe { Status{ t: time, - x0: IIR_STATE[0][0], - y0: IIR_STATE[0][2], - x1: IIR_STATE[1][0], - y1: IIR_STATE[1][2], + x0: iir_state[0][0], + y0: iir_state[0][2], + x1: iir_state[1][0], + y1: iir_state[1][2], }}; reply(socket, &s); } -#[derive(Serialize)] -struct Status { - t: u32, - x0: f32, - y0: f32, - x1: f32, - y1: f32 -} -*/ - #[exception] fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { panic!("HardFault at {:#?}", ef); From 2b9a02d98e049e30829f7527911d23192cf97e6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 30 May 2019 21:50:18 +0000 Subject: [PATCH 10/21] rtfm: status port --- src/main.rs | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/src/main.rs b/src/main.rs index dc7419b..adc03e8 100644 --- a/src/main.rs +++ b/src/main.rs @@ -514,6 +514,7 @@ macro_rules! create_socket { #[rtfm::app(device = stm32h7::stm32h7x3)] const APP: () = { static SPI: (stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5) = (); + static ETHERNET_PERIPH: (stm32::ETHERNET_MAC, stm32::ETHERNET_DMA, stm32::ETHERNET_MTL) = (); static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2]; static mut IIR_CH: [IIR; 2] = [ @@ -524,7 +525,6 @@ const APP: () = { y_max: SCALE }; 2]; - static ETHERNET_PERIPH: (stm32::ETHERNET_MAC, stm32::ETHERNET_DMA, stm32::ETHERNET_MTL) = (); #[link_section = ".sram3.eth"] static mut ETHERNET: eth::Device = eth::Device::new(); @@ -617,7 +617,7 @@ const APP: () = { } } - #[idle(resources = [ETHERNET, ETHERNET_PERIPH])] + #[idle(resources = [ETHERNET, ETHERNET_PERIPH, IIR_STATE])] fn idle(c: idle::Context) -> ! { let (MAC, DMA, MTL) = c.resources.ETHERNET_PERIPH; @@ -641,6 +641,7 @@ const APP: () = { let mut last = 0u32; let mut last_iter = rtfm::Instant::now(); //let mut server = Server::new(); + let mut iir_state: resources::IIR_STATE = c.resources.IIR_STATE; loop { // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } let mut time = last; @@ -652,9 +653,16 @@ const APP: () = { let socket = &mut *sockets.get::(tcp_handle0); if !(socket.is_open() || socket.is_listening()) { socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else if time > last && socket.can_send() { + } else if time != last && socket.can_send() { last = time; - //handle_status(socket, time); + let s = iir_state.lock(|iir_state| Status { + t: time, + x0: iir_state[0][0], + y0: iir_state[0][2], + x1: iir_state[1][0], + y1: iir_state[1][2] + }); + reply(socket, &s); } } { @@ -676,7 +684,7 @@ const APP: () = { } } - #[task(schedule = [tick])] + #[task(priority = 1, schedule = [tick])] fn tick(c: tick::Context) { static mut TIME: u32 = 0; *TIME += 1; @@ -686,13 +694,13 @@ const APP: () = { // seems to slow it down // #[link_section = ".data.spi1"] - #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 3)] + #[interrupt(resources = [SPI, IIR_STATE, IIR_CH], priority = 2)] fn SPI1(c: SPI1::Context) { #[cfg(feature = "bkpt")] cortex_m::asm::bkpt(); let (spi1, spi2, spi4, spi5) = c.resources.SPI; let iir_ch = c.resources.IIR_CH; - let iir_state = c.resources.IIR_STATE; + let mut iir_state = c.resources.IIR_STATE; let sr = spi1.sr.read(); if sr.eot().bit_is_set() { @@ -824,18 +832,6 @@ impl Server { } } -fn handle_status(socket: &mut net::socket::TcpSocket, time: u32, - iir_state: &[IIRState]) { - let s = unsafe { Status{ - t: time, - x0: iir_state[0][0], - y0: iir_state[0][2], - x1: iir_state[1][0], - y1: iir_state[1][2], - }}; - reply(socket, &s); -} - #[exception] fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { panic!("HardFault at {:#?}", ef); From 6c973038b4318dfed696a0959adeefad668b5dcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 3 Jun 2019 15:06:11 +0000 Subject: [PATCH 11/21] rtfm: command port --- src/main.rs | 131 +++++++++++++++++++++++++++------------------------- 1 file changed, 68 insertions(+), 63 deletions(-) diff --git a/src/main.rs b/src/main.rs index adc03e8..4fa4dbf 100644 --- a/src/main.rs +++ b/src/main.rs @@ -13,10 +13,10 @@ extern crate panic_semihosting; extern crate log; use core::ptr; -use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; +// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; use core::fmt::Write; -use cortex_m_rt::{exception}; -use stm32h7::stm32h7x3::{self as stm32, interrupt}; +use cortex_m_rt::exception; +use stm32h7::stm32h7x3 as pac; use heapless::{String, Vec, consts::*}; use smoltcp as net; @@ -55,7 +55,7 @@ mod build_info { // include!(concat!(env!("OUT_DIR"), "/built.rs")); } -fn pwr_setup(pwr: &stm32::PWR) { +fn pwr_setup(pwr: &pac::PWR) { // go to VOS1 voltage scale for high perf pwr.cr3.write(|w| w.scuen().set_bit() @@ -67,7 +67,7 @@ fn pwr_setup(pwr: &stm32::PWR) { while pwr.d3cr.read().vosrdy().bit_is_clear() {} } -fn rcc_reset(rcc: &stm32::RCC) { +fn rcc_reset(rcc: &pac::RCC) { // Reset all peripherals rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); rcc.ahb1rstr.write(|w| unsafe { w.bits(0)}); @@ -93,7 +93,7 @@ fn rcc_reset(rcc: &stm32::RCC) { rcc.apb4rstr.write(|w| unsafe { w.bits(0)}); } -fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { +fn rcc_pll_setup(rcc: &pac::RCC, flash: &pac::FLASH) { // Switch to HSI to mess with HSE rcc.cr.modify(|_, w| w.hsion().on()); while rcc.cr.read().hsirdy().is_not_ready() {} @@ -179,7 +179,7 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) { rcc.d3ccipr.modify(|_, w| w.spi6sel().pll2_q()); } -fn io_compensation_setup(syscfg: &stm32::SYSCFG) { +fn io_compensation_setup(syscfg: &pac::SYSCFG) { syscfg.cccsr.modify(|_, w| w.en().set_bit() .cs().clear_bit() @@ -188,8 +188,8 @@ fn io_compensation_setup(syscfg: &stm32::SYSCFG) { while syscfg.cccsr.read().ready().bit_is_clear() {} } -fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, - gpioe: &stm32::GPIOE, gpiof: &stm32::GPIOF, gpiog: &stm32::GPIOG) { +fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, + gpioe: &pac::GPIOE, gpiof: &pac::GPIOF, gpiog: &pac::GPIOG) { // FP_LED0 gpiod.otyper.modify(|_, w| w.ot5().push_pull()); gpiod.moder.modify(|_, w| w.moder5().output()); @@ -323,7 +323,7 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD, } // ADC0 -fn spi1_setup(spi1: &stm32::SPI1) { +fn spi1_setup(spi1: &pac::SPI1) { spi1.cfg1.modify(|_, w| w.mbr().div4() .dsize().bits(16 - 1) @@ -350,7 +350,7 @@ fn spi1_setup(spi1: &stm32::SPI1) { } // ADC1 -fn spi5_setup(spi5: &stm32::SPI5) { +fn spi5_setup(spi5: &pac::SPI5) { spi5.cfg1.modify(|_, w| w.mbr().div4() .dsize().bits(16 - 1) @@ -377,7 +377,7 @@ fn spi5_setup(spi5: &stm32::SPI5) { } // DAC0 -fn spi2_setup(spi2: &stm32::SPI2) { +fn spi2_setup(spi2: &pac::SPI2) { spi2.cfg1.modify(|_, w| w.mbr().div2() .dsize().bits(16 - 1) @@ -405,7 +405,7 @@ fn spi2_setup(spi2: &stm32::SPI2) { } // DAC1 -fn spi4_setup(spi4: &stm32::SPI4) { +fn spi4_setup(spi4: &pac::SPI4) { spi4.cfg1.modify(|_, w| w.mbr().div2() .dsize().bits(16 - 1) @@ -432,7 +432,7 @@ fn spi4_setup(spi4: &stm32::SPI4) { spi4.cr1.modify(|_, w| w.cstart().started()); } -fn tim2_setup(tim2: &stm32::TIM2) { +fn tim2_setup(tim2: &pac::TIM2) { tim2.psc.write(|w| unsafe { w.psc().bits(200 - 1) }); // from 200 MHz tim2.arr.write(|w| unsafe { w.bits(2 - 1) }); // µs tim2.dier.write(|w| w.ude().set_bit()); @@ -442,7 +442,7 @@ fn tim2_setup(tim2: &stm32::TIM2) { .cen().set_bit()); // enable } -fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { +fn dma1_setup(dma1: &pac::DMA1, dmamux1: &pac::DMAMUX1, ma: usize, pa0: usize, pa1: usize) { dma1.st[0].cr.modify(|_, w| w.en().clear_bit()); while dma1.st[0].cr.read().en().bit_is_set() {} @@ -495,7 +495,7 @@ const SCALE: f32 = ((1 << 15) - 1) as f32; #[link_section = ".sram1.datspi"] static mut DAT: u32 = 0x201; // EN | CSTART -static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); +// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true); const TCP_RX_BUFFER_SIZE: usize = 8192; const TCP_TX_BUFFER_SIZE: usize = 8192; @@ -513,8 +513,8 @@ macro_rules! create_socket { #[rtfm::app(device = stm32h7::stm32h7x3)] const APP: () = { - static SPI: (stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5) = (); - static ETHERNET_PERIPH: (stm32::ETHERNET_MAC, stm32::ETHERNET_DMA, stm32::ETHERNET_MTL) = (); + static SPI: (pac::SPI1, pac::SPI2, pac::SPI4, pac::SPI5) = (); + static ETHERNET_PERIPH: (pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL) = (); static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2]; static mut IIR_CH: [IIR; 2] = [ @@ -609,7 +609,7 @@ const APP: () = { eth::setup(&rcc, &dp.SYSCFG); eth::setup_pins(&dp.GPIOA, &dp.GPIOB, &dp.GPIOC, &dp.GPIOG); - c.schedule.tick(rtfm::Instant::now()).unwrap(); + // c.schedule.tick(rtfm::Instant::now()).unwrap(); init::LateResources { SPI: (spi1, spi2, spi4, spi5), @@ -617,7 +617,7 @@ const APP: () = { } } - #[idle(resources = [ETHERNET, ETHERNET_PERIPH, IIR_STATE])] + #[idle(resources = [ETHERNET, ETHERNET_PERIPH, IIR_STATE, IIR_CH])] fn idle(c: idle::Context) -> ! { let (MAC, DMA, MTL) = c.resources.ETHERNET_PERIPH; @@ -638,23 +638,26 @@ const APP: () = { create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle1); // unsafe { eth::enable_interrupt(DMA); } - let mut last = 0u32; - let mut last_iter = rtfm::Instant::now(); - //let mut server = Server::new(); + let mut time = 0u32; + let mut next_ms = rtfm::Instant::now(); + next_ms += 200_000.cycles(); + let mut server = Server::new(); let mut iir_state: resources::IIR_STATE = c.resources.IIR_STATE; + let mut iir_ch: resources::IIR_CH = c.resources.IIR_CH; loop { // if ETHERNET_PENDING.swap(false, Ordering::Relaxed) { } - let mut time = last; - if rtfm::Instant::now() >= last_iter + 200_000.cycles() { - last_iter += 200_000.cycles(); + let tick = rtfm::Instant::now() > next_ms; + if tick { + next_ms += 200_000.cycles(); time += 1; } { let socket = &mut *sockets.get::(tcp_handle0); - if !(socket.is_open() || socket.is_listening()) { + if socket.state() == net::socket::TcpState::CloseWait { + socket.close(); + } else if !(socket.is_open() || socket.is_listening()) { socket.listen(1234).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); - } else if time != last && socket.can_send() { - last = time; + } else if tick && socket.can_send() { let s = iir_state.lock(|iir_state| Status { t: time, x0: iir_state[0][0], @@ -662,15 +665,21 @@ const APP: () = { x1: iir_state[1][0], y1: iir_state[1][2] }); - reply(socket, &s); + json_reply(socket, &s); } } { let socket = &mut *sockets.get::(tcp_handle1); - if !(socket.is_open() || socket.is_listening()) { + if socket.state() == net::socket::TcpState::CloseWait { + socket.close(); + } else if !(socket.is_open() || socket.is_listening()) { socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); } else { - //server.handle_command(socket); + server.poll(socket, |req| { + if req.channel < 2 { + iir_ch.lock(|iir_ch| iir_ch[req.channel as usize] = req.iir); + } + }); } } @@ -772,23 +781,24 @@ struct Status { y1: f32 } -struct Server { - data: Vec, - discard: bool, -} - -fn reply(socket: &mut net::socket::TcpSocket, msg: &T) { +fn json_reply(socket: &mut net::socket::TcpSocket, msg: &T) { let mut u: String = to_string(msg).unwrap(); u.push('\n').unwrap(); socket.write_str(&u).unwrap(); } +struct Server { + data: Vec, + discard: bool, +} + impl Server { fn new() -> Self { Self { data: Vec::new(), discard: false } } - fn handle_command(&mut self, socket: &mut net::socket::TcpSocket) { + fn poll( + &mut self, socket: &mut net::socket::TcpSocket, f: F) { while socket.can_recv() { let found = socket.recv(|buf| { let (len, found) = match buf.iter().position(|&c| c as char == '\n') { @@ -803,31 +813,26 @@ impl Server { } (len, found) }).unwrap(); - if !found { - continue; - } - let resp = if self.discard { - self.discard = false; - Response{ code: 520, message: "command buffer overflow" } - } else { - match from_slice::(&self.data) { - Ok(request) => { - if request.channel > 1 { - Response{ code: 530, message: "invalid channel" } - } else { - //unsafe { IIR_CH[request.channel as usize] = request.iir; }; - Response{ code: 200, message: "ok" } - } - }, - Err(err) => { - warn!("parse error {:?}", err); - Response{ code: 550, message: "parse error" } - }, + if found { + if self.discard { + self.discard = false; + json_reply(socket, &Response { code: 520, message: "command buffer overflow" }); + } else { + let r = from_slice::(&self.data); + self.data.clear(); + match r { + Ok(res) => { + f(&res); + json_reply(socket, &Response{ code: 200, message: "ok" }); + return; + }, + Err(err) => { + warn!("parse error {:?}", err); + json_reply(socket, &Response { code: 550, message: "parse error" }); + }, + } } - }; - self.data.clear(); - reply(socket, &resp); - socket.close(); + } } } } From 91a7dda633c623341f030854049b22e0e9d609db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 3 Jun 2019 15:14:04 +0000 Subject: [PATCH 12/21] cargo: update --- Cargo.lock | 26 +++++++++++++------------- Cargo.toml | 3 ++- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 20e28b8..8d98755 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -99,18 +99,18 @@ dependencies = [ [[package]] name = "cortex-m-rtfm" version = "0.5.0-alpha.1" -source = "git+https://github.com/japaric/cortex-m-rtfm#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" +source = "git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" dependencies = [ "cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", - "cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm)", + "cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "cortex-m-rtfm-macros" version = "0.5.0-alpha.1" -source = "git+https://github.com/japaric/cortex-m-rtfm#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" +source = "git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" dependencies = [ "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", @@ -269,10 +269,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "serde" -version = "1.0.91" +version = "1.0.92" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "serde_derive 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)", + "serde_derive 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -281,12 +281,12 @@ version = "0.0.1" source = "git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9#82fdca9eb08183f00480eea289e809e5dd37e9fe" dependencies = [ "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", - "serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)", + "serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "serde_derive" -version = "1.0.91" +version = "1.0.92" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", @@ -311,12 +311,12 @@ dependencies = [ "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", - "cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm)", + "cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", "panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)", "panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)", - "serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)", + "serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", "serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)", "smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", "stm32h7 0.7.0", @@ -383,8 +383,8 @@ dependencies = [ "checksum cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "584a62cf37ddd834b8bfc21317bf3396915844298bf346dd1f4ca0572180ac7f" "checksum cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)" = "7e1ccc9052352415ec4e3f762f4541098d012016f9354a1a5b2dede39b67f426" "checksum cortex-m-rt-macros 0.1.5 (registry+https://github.com/rust-lang/crates.io-index)" = "d7ae692573e0acccb1579fef1abf5a5bf1d2f3f0149a22b16870ec9309aee25f" -"checksum cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm)" = "" -"checksum cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm)" = "" +"checksum cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "" +"checksum cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "" "checksum cortex-m-semihosting 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)" = "165f3f86f4d1031351a6c9dc8d5a3f8fae2050f9dd6ef925e3d675c232cc0e46" "checksum generic-array 0.11.1 (registry+https://github.com/rust-lang/crates.io-index)" = "8107dafa78c80c848b71b60133954b4a58609a3a1a5f9af037ecc7f67280f369" "checksum generic-array 0.12.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3c0f28c2f5bfb5960175af447a2da7c18900693738343dc896ffbcabd9839592" @@ -405,9 +405,9 @@ dependencies = [ "checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a" "checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403" "checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" -"checksum serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "a72e9b96fa45ce22a4bc23da3858dfccfd60acd28a25bcd328a98fdd6bea43fd" +"checksum serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)" = "32746bf0f26eab52f06af0d0aa1984f641341d06d8d673c693871da2d188c9be" "checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)" = "" -"checksum serde_derive 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "101b495b109a3e3ca8c4cbe44cf62391527cdfb6ba15821c5ce80bcd5ea23f9f" +"checksum serde_derive 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)" = "46a3223d0c9ba936b61c0d2e3e559e3217dbfb8d65d06d26e8b3c25de38bae3e" "checksum smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fef582369edb298c6c41319a544ca9c4e83622f226055ccfcb35974fbb55ed34" "checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" "checksum syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)" = "a1393e4a97a19c01e900df2aec855a29f71cf02c402e2f443b8d2747c25c5dbe" diff --git a/Cargo.toml b/Cargo.toml index 10adbb4..9601e31 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -48,13 +48,14 @@ features = ["stm32h7x3", "rt"] [dependencies.smoltcp] #git = "https://github.com/m-labs/smoltcp.git" -#rev = "cd893e6" +#rev = "0f61443" version = "0.5" features = ["proto-ipv4", "socket-tcp"] default-features = false [dependencies.cortex-m-rtfm] git = "https://github.com/japaric/cortex-m-rtfm" +rev = "fafeeb2" features = ["timer-queue"] [features] From ee15c27dd95dae1922b7465d0254177ba815782e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 3 Jun 2019 15:54:35 +0000 Subject: [PATCH 13/21] make json poll generic --- src/main.rs | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/main.rs b/src/main.rs index 4fa4dbf..28b19bb 100644 --- a/src/main.rs +++ b/src/main.rs @@ -21,7 +21,7 @@ use heapless::{String, Vec, consts::*}; use smoltcp as net; -use serde::{Serialize, Deserialize}; +use serde::{Serialize, Deserialize, de::DeserializeOwned}; use serde_json_core::{ser::to_string, de::from_slice}; mod eth; @@ -675,7 +675,7 @@ const APP: () = { } else if !(socket.is_open() || socket.is_listening()) { socket.listen(1235).unwrap_or_else(|e| warn!("TCP listen error: {:?}", e)); } else { - server.poll(socket, |req| { + server.poll(socket, |req: &Request| { if req.channel < 2 { iir_ch.lock(|iir_ch| iir_ch[req.channel as usize] = req.iir); } @@ -797,8 +797,11 @@ impl Server { Self { data: Vec::new(), discard: false } } - fn poll( - &mut self, socket: &mut net::socket::TcpSocket, f: F) { + fn poll(&mut self, socket: &mut net::socket::TcpSocket, f: F) + where + T: DeserializeOwned, + F: FnOnce(&T), + { while socket.can_recv() { let found = socket.recv(|buf| { let (len, found) = match buf.iter().position(|&c| c as char == '\n') { @@ -818,7 +821,7 @@ impl Server { self.discard = false; json_reply(socket, &Response { code: 520, message: "command buffer overflow" }); } else { - let r = from_slice::(&self.data); + let r = from_slice::(&self.data); self.data.clear(); match r { Ok(res) => { From a8e17407592e6ea87847eb2bac846f8d3133e17d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 3 Jun 2019 17:08:21 +0000 Subject: [PATCH 14/21] parametrize poll return --- src/main.rs | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main.rs b/src/main.rs index 28b19bb..a0ee5e5 100644 --- a/src/main.rs +++ b/src/main.rs @@ -797,10 +797,10 @@ impl Server { Self { data: Vec::new(), discard: false } } - fn poll(&mut self, socket: &mut net::socket::TcpSocket, f: F) + fn poll(&mut self, socket: &mut net::socket::TcpSocket, f: F) -> Option where T: DeserializeOwned, - F: FnOnce(&T), + F: FnOnce(&T) -> R, { while socket.can_recv() { let found = socket.recv(|buf| { @@ -820,14 +820,15 @@ impl Server { if self.discard { self.discard = false; json_reply(socket, &Response { code: 520, message: "command buffer overflow" }); + self.data.clear(); } else { let r = from_slice::(&self.data); self.data.clear(); match r { Ok(res) => { - f(&res); - json_reply(socket, &Response{ code: 200, message: "ok" }); - return; + let r = f(&res); + json_reply(socket, &Response { code: 200, message: "ok" }); + return Some(r); }, Err(err) => { warn!("parse error {:?}", err); @@ -837,6 +838,7 @@ impl Server { } } } + None } } From 5204a3169bec916d1a4c14b22a363031f5a70c7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 4 Jun 2019 09:26:28 +0000 Subject: [PATCH 15/21] gpio: use odr variants --- src/main.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/main.rs b/src/main.rs index a0ee5e5..ce3f3d8 100644 --- a/src/main.rs +++ b/src/main.rs @@ -193,22 +193,22 @@ fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, // FP_LED0 gpiod.otyper.modify(|_, w| w.ot5().push_pull()); gpiod.moder.modify(|_, w| w.moder5().output()); - gpiod.odr.modify(|_, w| w.odr5().clear_bit()); + gpiod.odr.modify(|_, w| w.odr5().low()); // FP_LED1 gpiod.otyper.modify(|_, w| w.ot6().push_pull()); gpiod.moder.modify(|_, w| w.moder6().output()); - gpiod.odr.modify(|_, w| w.odr6().clear_bit()); + gpiod.odr.modify(|_, w| w.odr6().low()); // LED_FP2 gpiog.otyper.modify(|_, w| w.ot4().push_pull()); gpiog.moder.modify(|_, w| w.moder4().output()); - gpiog.odr.modify(|_, w| w.odr4().clear_bit()); + gpiog.odr.modify(|_, w| w.odr4().low()); // LED_FP3 gpiod.otyper.modify(|_, w| w.ot12().push_pull()); gpiod.moder.modify(|_, w| w.moder12().output()); - gpiod.odr.modify(|_, w| w.odr12().clear_bit()); + gpiod.odr.modify(|_, w| w.odr12().low()); // AFE0_A0,1: PG2,PG3 gpiog.otyper.modify(|_, w| @@ -220,8 +220,8 @@ fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, .moder3().output() ); gpiog.odr.modify(|_, w| - w.odr2().clear_bit() - .odr3().clear_bit() + w.odr2().low() + .odr3().low() ); // ADC0 @@ -261,12 +261,12 @@ fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, // DAC0_LDAC: PE11 gpioe.moder.modify(|_, w| w.moder11().output()); gpioe.otyper.modify(|_, w| w.ot11().push_pull()); - gpioe.odr.modify(|_, w| w.odr11().clear_bit()); + gpioe.odr.modify(|_, w| w.odr11().low()); // DAC_CLR: PE12 gpioe.moder.modify(|_, w| w.moder12().output()); gpioe.otyper.modify(|_, w| w.ot12().push_pull()); - gpioe.odr.modify(|_, w| w.odr12().set_bit()); + gpioe.odr.modify(|_, w| w.odr12().high()); // AFE1_A0,1: PD14,PD15 gpiod.otyper.modify(|_, w| @@ -278,8 +278,8 @@ fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, .moder15().output() ); gpiod.odr.modify(|_, w| - w.odr14().clear_bit() - .odr15().clear_bit() + w.odr14().low() + .odr15().low() ); // ADC1 @@ -319,7 +319,7 @@ fn gpio_setup(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, gpiod: &pac::GPIOD, // DAC1_LDAC: PE15 gpioe.moder.modify(|_, w| w.moder15().output()); gpioe.otyper.modify(|_, w| w.ot15().push_pull()); - gpioe.odr.modify(|_, w| w.odr15().clear_bit()); + gpioe.odr.modify(|_, w| w.odr15().low()); } // ADC0 @@ -346,7 +346,7 @@ fn spi1_setup(spi1: &pac::SPI1) { .mssi().bits(6) ); spi1.cr2.modify(|_, w| w.tsize().bits(1)); - spi1.cr1.write(|w| w.spe().set_bit()); + spi1.cr1.write(|w| w.spe().enabled()); } // ADC1 @@ -373,7 +373,7 @@ fn spi5_setup(spi5: &pac::SPI5) { .mssi().bits(6) ); spi5.cr2.modify(|_, w| w.tsize().bits(1)); - spi5.cr1.write(|w| w.spe().set_bit()); + spi5.cr1.write(|w| w.spe().enabled()); } // DAC0 From a8e2d616bb3cd3ef89a8e12413114777ba9e9c55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 7 Jun 2019 11:17:21 +0200 Subject: [PATCH 16/21] bump heapless --- Cargo.lock | 36 ++++++++---------------------------- Cargo.toml | 4 ++-- 2 files changed, 10 insertions(+), 30 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 8d98755..48d4d45 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -32,7 +32,7 @@ dependencies = [ [[package]] name = "bitflags" -version = "1.0.4" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] @@ -125,14 +125,6 @@ dependencies = [ "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", ] -[[package]] -name = "generic-array" -version = "0.11.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -dependencies = [ - "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - [[package]] name = "generic-array" version = "0.12.0" @@ -157,16 +149,6 @@ dependencies = [ "byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)", ] -[[package]] -name = "heapless" -version = "0.4.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -dependencies = [ - "as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", - "generic-array 0.11.1 (registry+https://github.com/rust-lang/crates.io-index)", - "hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", -] - [[package]] name = "heapless" version = "0.5.0-alpha.2" @@ -278,9 +260,9 @@ dependencies = [ [[package]] name = "serde-json-core" version = "0.0.1" -source = "git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9#82fdca9eb08183f00480eea289e809e5dd37e9fe" +source = "git+https://github.com/quartiq/serde-json-core.git?rev=fc764de#fc764deb8dfb82e5cfcc6c5059d8d5c3031e0591" dependencies = [ - "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", + "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", "serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -299,7 +281,7 @@ name = "smoltcp" version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)", + "bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)", "byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)", "managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -312,12 +294,12 @@ dependencies = [ "cortex-m-log 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", - "heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)", + "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", "panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)", "panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)", "serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", - "serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)", + "serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)", "smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", "stm32h7 0.7.0", ] @@ -375,7 +357,7 @@ dependencies = [ "checksum aligned 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "d3a316c7ea8e1e9ece54862c992def5a7ac14de9f5832b69d71760680efeeefa" "checksum as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "293dac66b274fab06f95e7efb05ec439a6b70136081ea522d270bc351ae5bb27" "checksum bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)" = "a3caf393d93b2d453e80638d0674597020cef3382ada454faacd43d1a55a735a" -"checksum bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)" = "228047a76f468627ca71776ecdebd732a3423081fcf5125585bcd7c49886ce12" +"checksum bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3d155346769a6855b86399e9bc3814ab343cd3d62c7e985113d46a0ec3c281fd" "checksum byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "a019b10a2a7cdeb292db131fc8113e57ea2a908f6e7894b0c3c671893b65dbeb" "checksum cfg-if 0.1.9 (registry+https://github.com/rust-lang/crates.io-index)" = "b486ce3ccf7ffd79fdeb678eac06a9e6c09fc88d33836340becb8fffe87c5e33" "checksum cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)" = "3c0b159a1e8306949579de3698c841dba58058197b65c60807194e4fa1e7a554" @@ -386,11 +368,9 @@ dependencies = [ "checksum cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "" "checksum cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "" "checksum cortex-m-semihosting 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)" = "165f3f86f4d1031351a6c9dc8d5a3f8fae2050f9dd6ef925e3d675c232cc0e46" -"checksum generic-array 0.11.1 (registry+https://github.com/rust-lang/crates.io-index)" = "8107dafa78c80c848b71b60133954b4a58609a3a1a5f9af037ecc7f67280f369" "checksum generic-array 0.12.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3c0f28c2f5bfb5960175af447a2da7c18900693738343dc896ffbcabd9839592" "checksum generic-array 0.13.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d3904420fad470d07ec9e4dbac00c2dc46765d3c4eb6cd1d9bb4d9c8a09c5f6" "checksum hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "12d790435639c06a7b798af9e1e331ae245b7ef915b92f70a39b4cf8c00686af" -"checksum heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)" = "e1ae80bbc62401ae8096976857172507cadbd2200f36670e5144634360a05959" "checksum heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)" = "c50e9f50ed4098bca126410960080738c3dd4cbea45812c15cf8aa02a9cfded1" "checksum log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c84ec4b527950aa83a329754b01dbe3f58361d1c5efacd1f6d68c494d08a17c6" "checksum managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6" @@ -406,7 +386,7 @@ dependencies = [ "checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403" "checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" "checksum serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)" = "32746bf0f26eab52f06af0d0aa1984f641341d06d8d673c693871da2d188c9be" -"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)" = "" +"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)" = "" "checksum serde_derive 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)" = "46a3223d0c9ba936b61c0d2e3e559e3217dbfb8d65d06d26e8b3c25de38bae3e" "checksum smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fef582369edb298c6c41319a544ca9c4e83622f226055ccfcb35974fbb55ed34" "checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" diff --git a/Cargo.toml b/Cargo.toml index 9601e31..3fdd336 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -34,12 +34,12 @@ log = "0.4" panic-abort = "0.3" panic-semihosting = { version = "0.5.2", optional = true } serde = { version = "1.0", features = ["derive"], default-features = false } -heapless = { version = "0.4" } +heapless = { version = "0.5.0-alpha.2" } [dependencies.serde-json-core] # version = "0.0" git = "https://github.com/quartiq/serde-json-core.git" -rev = "82fdca9" +rev = "fc764de" [dependencies.stm32h7] path = "../stm32-rs/stm32h7" From 8ee09500054e2b88e8ec3dfd45f1691cd98c3493 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 7 Jun 2019 11:26:24 +0200 Subject: [PATCH 17/21] panic: turn red leds on --- src/main.rs | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main.rs b/src/main.rs index ce3f3d8..9b4c25b 100644 --- a/src/main.rs +++ b/src/main.rs @@ -4,8 +4,16 @@ // Enable returning `!` #![feature(never_type)] +#[inline(never)] +#[panic_handler] #[cfg(not(feature = "semihosting"))] -extern crate panic_abort; +fn panic(_info: &core::panic::PanicInfo) -> ! { + let dp = unsafe { pac::Peripherals::steal() }; + dp.GPIOD.odr.modify(|_, w| w.odr6().high()); // FP_LED_1 + dp.GPIOG.odr.modify(|_, w| w.odr4().high()); // FP_LED_3 + loop { core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst); } +} + #[cfg(feature = "semihosting")] extern crate panic_semihosting; From 9b6ef68eac5df5af3091eef43ada5558785c15d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 7 Jun 2019 14:28:22 +0000 Subject: [PATCH 18/21] fix panic handler --- src/main.rs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main.rs b/src/main.rs index 9b4c25b..56cfcd1 100644 --- a/src/main.rs +++ b/src/main.rs @@ -8,9 +8,8 @@ #[panic_handler] #[cfg(not(feature = "semihosting"))] fn panic(_info: &core::panic::PanicInfo) -> ! { - let dp = unsafe { pac::Peripherals::steal() }; - dp.GPIOD.odr.modify(|_, w| w.odr6().high()); // FP_LED_1 - dp.GPIOG.odr.modify(|_, w| w.odr4().high()); // FP_LED_3 + let gpiod = unsafe { &*pac::GPIOD::ptr() }; + gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3 loop { core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst); } } From dd981ed850859ceec9770a409f8a2967d4061988 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 10 Jun 2019 00:29:20 +0200 Subject: [PATCH 19/21] panic: abort, not halt --- Cargo.lock | 7 ------- Cargo.toml | 1 - src/main.rs | 3 ++- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 48d4d45..66f25be 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -172,11 +172,6 @@ name = "managed" version = "0.7.1" source = "registry+https://github.com/rust-lang/crates.io-index" -[[package]] -name = "panic-abort" -version = "0.3.1" -source = "registry+https://github.com/rust-lang/crates.io-index" - [[package]] name = "panic-semihosting" version = "0.5.2" @@ -296,7 +291,6 @@ dependencies = [ "cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", - "panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)", "panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)", "serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", "serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)", @@ -374,7 +368,6 @@ dependencies = [ "checksum heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)" = "c50e9f50ed4098bca126410960080738c3dd4cbea45812c15cf8aa02a9cfded1" "checksum log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c84ec4b527950aa83a329754b01dbe3f58361d1c5efacd1f6d68c494d08a17c6" "checksum managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6" -"checksum panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "2c14a66511ed17b6a8b4256b868d7fd207836d891db15eea5195dbcaf87e630f" "checksum panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)" = "97cfb37c1d3b5f0cc18bf14485018cccd13bdd24f7b5bfd456c1d8760afef824" "checksum proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)" = "cf3d2011ab5c909338f7887f4fc896d35932e29146c12c8d01da6b22a80ba759" "checksum quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)" = "faf4799c5d274f3868a4aae320a0a182cbd2baee377b378f080e16a23e9d80db" diff --git a/Cargo.toml b/Cargo.toml index 3fdd336..e060c21 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -31,7 +31,6 @@ cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] } cortex-m-rt = { version = "0.6", features = ["device"] } cortex-m-log = { version = "0.5", features = ["log-integration"] } log = "0.4" -panic-abort = "0.3" panic-semihosting = { version = "0.5.2", optional = true } serde = { version = "1.0", features = ["derive"], default-features = false } heapless = { version = "0.5.0-alpha.2" } diff --git a/src/main.rs b/src/main.rs index 56cfcd1..dea0121 100644 --- a/src/main.rs +++ b/src/main.rs @@ -3,6 +3,7 @@ #![feature(asm)] // Enable returning `!` #![feature(never_type)] +#![feature(core_intrinsics)] #[inline(never)] #[panic_handler] @@ -10,7 +11,7 @@ fn panic(_info: &core::panic::PanicInfo) -> ! { let gpiod = unsafe { &*pac::GPIOD::ptr() }; gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3 - loop { core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst); } + unsafe { core::intrinsics::abort(); } } #[cfg(feature = "semihosting")] From 737dc9ee491a6ac4b78ff5fe89d4a923b9792905 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 15 Jul 2019 16:00:55 +0000 Subject: [PATCH 20/21] cargo: update --- Cargo.lock | 84 +++++++++++++++++++++++++++--------------------------- Cargo.toml | 4 +-- 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 66f25be..3fc0199 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -18,7 +18,7 @@ name = "as-slice" version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "generic-array 0.12.0 (registry+https://github.com/rust-lang/crates.io-index)", + "generic-array 0.12.3 (registry+https://github.com/rust-lang/crates.io-index)", "stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -37,7 +37,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "byteorder" -version = "1.3.1" +version = "1.3.2" source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] @@ -73,12 +73,12 @@ source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "cortex-m 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-semihosting 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)", - "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)", + "log 0.4.7 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "cortex-m-rt" -version = "0.6.8" +version = "0.6.9" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "cortex-m-rt-macros 0.1.5 (registry+https://github.com/rust-lang/crates.io-index)", @@ -91,9 +91,9 @@ version = "0.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", "rand 0.5.6 (registry+https://github.com/rust-lang/crates.io-index)", - "syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.39 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -102,9 +102,9 @@ version = "0.5.0-alpha.1" source = "git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" dependencies = [ "cortex-m 0.5.10 (registry+https://github.com/rust-lang/crates.io-index)", - "cortex-m-rt 0.6.8 (registry+https://github.com/rust-lang/crates.io-index)", + "cortex-m-rt 0.6.9 (registry+https://github.com/rust-lang/crates.io-index)", "cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)", - "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", + "heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -113,8 +113,8 @@ version = "0.5.0-alpha.1" source = "git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2#fafeeb27270ef24fc3852711c6032f65aa7dbcc0" dependencies = [ "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", - "syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.39 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -127,7 +127,7 @@ dependencies = [ [[package]] name = "generic-array" -version = "0.12.0" +version = "0.12.3" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -135,7 +135,7 @@ dependencies = [ [[package]] name = "generic-array" -version = "0.13.0" +version = "0.13.2" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)", @@ -146,22 +146,22 @@ name = "hash32" version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "byteorder 1.3.1 (registry+https://github.com/rust-lang/crates.io-index)", + "byteorder 1.3.2 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "heapless" -version = "0.5.0-alpha.2" +version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "as-slice 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", - "generic-array 0.13.0 (registry+https://github.com/rust-lang/crates.io-index)", + "generic-array 0.13.2 (registry+https://github.com/rust-lang/crates.io-index)", "hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "log" -version = "0.4.6" +version = "0.4.7" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "cfg-if 0.1.9 (registry+https://github.com/rust-lang/crates.io-index)", @@ -191,7 +191,7 @@ dependencies = [ [[package]] name = "quote" -version = "0.6.12" +version = "0.6.13" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", @@ -246,10 +246,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] name = "serde" -version = "1.0.92" +version = "1.0.94" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "serde_derive 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", + "serde_derive 1.0.94 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -257,18 +257,18 @@ name = "serde-json-core" version = "0.0.1" source = "git+https://github.com/quartiq/serde-json-core.git?rev=fc764de#fc764deb8dfb82e5cfcc6c5059d8d5c3031e0591" dependencies = [ - "heapless 0.5.0-alpha.2 (registry+https://github.com/rust-lang/crates.io-index)", - "serde 1.0.92 (registry+https://github.com/rust-lang/crates.io-index)", + "heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)", + "serde 1.0.94 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "serde_derive" -version = "1.0.92" +version = "1.0.94" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)", - "syn 0.15.34 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 0.15.39 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -277,7 +277,7 @@ version = "0.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "bitflags 1.1.0 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(registry+https://github.com/rust-lang/crates.io-index)" = "cf3d2011ab5c909338f7887f4fc896d35932e29146c12c8d01da6b22a80ba759" @@ -378,12 +379,13 @@ dependencies = [ "checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a" "checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403" "checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" -"checksum serde 1.0.94 (registry+https://github.com/rust-lang/crates.io-index)" = "076a696fdea89c19d3baed462576b8f6d663064414b5c793642da8dfeb99475b" +"checksum serde 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "7fe5626ac617da2f2d9c48af5515a21d5a480dbd151e01bb1c355e26a3e68113" "checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)" = "" -"checksum serde_derive 1.0.94 (registry+https://github.com/rust-lang/crates.io-index)" = "ef45eb79d6463b22f5f9e16d283798b7c0175ba6050bc25c1a946c122727fe7b" +"checksum serde_derive 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "01e69e1b8a631f245467ee275b8c757b818653c6d704cdbcaeb56b56767b529c" "checksum smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fef582369edb298c6c41319a544ca9c4e83622f226055ccfcb35974fbb55ed34" "checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8" -"checksum syn 0.15.39 (registry+https://github.com/rust-lang/crates.io-index)" = "b4d960b829a55e56db167e861ddb43602c003c7be0bee1d345021703fac2fb7c" +"checksum stm32h7 0.8.0 (registry+https://github.com/rust-lang/crates.io-index)" = "63001af508d3332bd2dd81d4212b69e10f45e8f5435b7dab5def36178b9c1c17" +"checksum syn 0.15.42 (registry+https://github.com/rust-lang/crates.io-index)" = "eadc09306ca51a40555dd6fc2b415538e9e18bc9f870e47b1a524a79fe2dcf5e" "checksum typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "612d636f949607bdf9b123b4a6f6d966dedf3ff669f7f045890d3a4a73948169" "checksum unicode-xid 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fc72304796d0818e357ead4e000d19c9c174ab23dc11093ac919054d20a6a7fc" "checksum vcell 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "45c297f0afb6928cd08ab1ff9d95e99392595ea25ae1b5ecf822ff8764e57a0d" diff --git a/Cargo.toml b/Cargo.toml index 4b66aa7..0e87142 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -41,9 +41,8 @@ git = "https://github.com/quartiq/serde-json-core.git" rev = "fc764de" [dependencies.stm32h7] -path = "../stm32-rs/stm32h7" -# version = "0.7" -features = ["stm32h7x3", "rt"] +version = "0.8" +features = ["stm32h743", "rt"] [dependencies.smoltcp] #git = "https://github.com/m-labs/smoltcp.git" diff --git a/src/eth.rs b/src/eth.rs index f95ebcf..211fa16 100644 --- a/src/eth.rs +++ b/src/eth.rs @@ -1,5 +1,5 @@ use core::{slice, cmp}; -use stm32h7::stm32h7x3 as stm32; +use stm32h7::stm32h743 as pac; use smoltcp::Result; use smoltcp::time::Instant; use smoltcp::wire::EthernetAddress; @@ -86,7 +86,7 @@ use self::cr_consts::*; const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102; -pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) { +pub fn setup(rcc: &pac::RCC, syscfg: &pac::SYSCFG) { rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit()); rcc.ahb1enr.modify(|_, w| { w.eth1macen().set_bit() @@ -98,8 +98,8 @@ pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) { //rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit()); } -pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, - gpioc: &stm32::GPIOC, gpiog: &stm32::GPIOG) { +pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB, + gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) { // PA1 RMII_REF_CLK gpioa.moder.modify(|_, w| w.moder1().alternate()); gpioa.afrl.modify(|_, w| w.afr1().af11()); @@ -140,7 +140,7 @@ pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, const PHY_ADDR: u8 = 0; -fn phy_read(reg_addr: u8, mac: &stm32::ETHERNET_MAC) -> u16 { +fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 { while mac.macmdioar.read().mb().bit_is_set() {} mac.macmdioar.modify(|_, w| unsafe { w @@ -154,7 +154,7 @@ fn phy_read(reg_addr: u8, mac: &stm32::ETHERNET_MAC) -> u16 { mac.macmdiodr.read().md().bits() } -fn phy_write(reg_addr: u8, reg_data: u16, mac: &stm32::ETHERNET_MAC) { +fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) { while mac.macmdioar.read().mb().bit_is_set() {} mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) }); mac.macmdioar.modify(|_, w| unsafe { @@ -169,7 +169,7 @@ fn phy_write(reg_addr: u8, reg_data: u16, mac: &stm32::ETHERNET_MAC) { } // Writes a value to an extended PHY register in MMD address space -fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &stm32::ETHERNET_MAC) { +fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) { phy_write(PHY_REG_CTL, 0x0003, mac); // set address phy_write(PHY_REG_ADDAR, reg_addr, mac); phy_write(PHY_REG_CTL, 0x4003, mac); // set data @@ -192,7 +192,7 @@ impl RxRing { } } - unsafe fn init(&mut self, dma: &stm32::ETHERNET_DMA) { + unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) { assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0); @@ -245,7 +245,7 @@ impl RxRing { let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; assert_eq!(addr & 0x3, 0); - let dma = unsafe { stm32::Peripherals::steal().ETHERNET_DMA }; + let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA }; dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) }); self.cur_desc = self.next_desc(); @@ -268,7 +268,7 @@ impl TxRing { } } - unsafe fn init(&mut self, dma: &stm32::ETHERNET_DMA) { + unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) { assert_eq!(self.desc_buf[0].len() % 4, 0); assert_eq!(self.pkt_buf[0].len() % 4, 0); @@ -314,7 +314,7 @@ impl TxRing { let addr = &self.desc_buf[self.cur_desc] as *const _ as u32; assert_eq!(addr & 0x3, 0); - let dma = unsafe { stm32::Peripherals::steal().ETHERNET_DMA }; + let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA }; dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) }); } } @@ -331,9 +331,9 @@ impl Device { // After `init` is called, `Device` shall not be moved. pub unsafe fn init(&mut self, mac: EthernetAddress, - eth_mac: &stm32::ETHERNET_MAC, - eth_dma: &stm32::ETHERNET_DMA, - eth_mtl: &stm32::ETHERNET_MTL, + eth_mac: &pac::ETHERNET_MAC, + eth_dma: &pac::ETHERNET_DMA, + eth_mtl: &pac::ETHERNET_MTL, ) { eth_dma.dmamr.modify(|_, w| w.swr().set_bit()); while eth_dma.dmamr.read().swr().bit_is_set() {} @@ -558,7 +558,7 @@ impl<'a> phy::TxToken for TxToken<'a> { } } -pub unsafe fn interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) { +pub unsafe fn interrupt_handler(eth_dma: &pac::ETHERNET_DMA) { eth_dma.dmacsr.write(|w| w .nis().set_bit() @@ -567,7 +567,7 @@ pub unsafe fn interrupt_handler(eth_dma: &stm32::ETHERNET_DMA) { ); } -pub unsafe fn enable_interrupt(eth_dma: &stm32::ETHERNET_DMA) { +pub unsafe fn enable_interrupt(eth_dma: &pac::ETHERNET_DMA) { eth_dma.dmacier.modify(|_, w| w .nie().set_bit() diff --git a/src/main.rs b/src/main.rs index dea0121..37faf99 100644 --- a/src/main.rs +++ b/src/main.rs @@ -24,7 +24,7 @@ use core::ptr; // use core::sync::atomic::{AtomicU32, AtomicBool, Ordering}; use core::fmt::Write; use cortex_m_rt::exception; -use stm32h7::stm32h7x3 as pac; +use stm32h7::stm32h743 as pac; use heapless::{String, Vec, consts::*}; use smoltcp as net; @@ -441,7 +441,7 @@ fn spi4_setup(spi4: &pac::SPI4) { } fn tim2_setup(tim2: &pac::TIM2) { - tim2.psc.write(|w| unsafe { w.psc().bits(200 - 1) }); // from 200 MHz + tim2.psc.write(|w| w.psc().bits(200 - 1)); // from 200 MHz tim2.arr.write(|w| unsafe { w.bits(2 - 1) }); // µs tim2.dier.write(|w| w.ude().set_bit()); tim2.egr.write(|w| w.ug().set_bit()); @@ -519,7 +519,7 @@ macro_rules! create_socket { ) } -#[rtfm::app(device = stm32h7::stm32h7x3)] +#[rtfm::app(device = stm32h7::stm32h743)] const APP: () = { static SPI: (pac::SPI1, pac::SPI2, pac::SPI4, pac::SPI5) = (); static ETHERNET_PERIPH: (pac::ETHERNET_MAC, pac::ETHERNET_DMA, pac::ETHERNET_MTL) = ();