Merge branch 'rtfm'
* rtfm: (21 commits) cargo: bump stm32h7, misc cargo: update panic: abort, not halt fix panic handler panic: turn red leds on bump heapless gpio: use odr variants parametrize poll return make json poll generic cargo: update rtfm: command port rtfm: status port rtfm: move ethernet into idle rtfm: continue work use rtfm [wip] ethernet peripheral ownership, cs pac: rcc pac updates (~0.8) stm32h7 svd and pac changes new stm32h7 pac ...master
commit
52e59b69c2
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|
||||
"checksum cortex-m-rt 0.6.10 (registry+https://github.com/rust-lang/crates.io-index)" = "17805910e3ecf029bdbfcc42b7384d9e3d9e5626153fa810002c1ef9839338ac"
|
||||
"checksum cortex-m-rt-macros 0.1.5 (registry+https://github.com/rust-lang/crates.io-index)" = "d7ae692573e0acccb1579fef1abf5a5bf1d2f3f0149a22b16870ec9309aee25f"
|
||||
"checksum cortex-m-rtfm 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "<none>"
|
||||
"checksum cortex-m-rtfm-macros 0.5.0-alpha.1 (git+https://github.com/japaric/cortex-m-rtfm?rev=fafeeb2)" = "<none>"
|
||||
"checksum cortex-m-semihosting 0.3.3 (registry+https://github.com/rust-lang/crates.io-index)" = "165f3f86f4d1031351a6c9dc8d5a3f8fae2050f9dd6ef925e3d675c232cc0e46"
|
||||
"checksum generic-array 0.11.1 (registry+https://github.com/rust-lang/crates.io-index)" = "8107dafa78c80c848b71b60133954b4a58609a3a1a5f9af037ecc7f67280f369"
|
||||
"checksum generic-array 0.12.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3c0f28c2f5bfb5960175af447a2da7c18900693738343dc896ffbcabd9839592"
|
||||
"checksum generic-array 0.12.3 (registry+https://github.com/rust-lang/crates.io-index)" = "c68f0274ae0e023facc3c97b2e00f076be70e254bc851d972503b328db79b2ec"
|
||||
"checksum generic-array 0.13.2 (registry+https://github.com/rust-lang/crates.io-index)" = "0ed1e761351b56f54eb9dcd0cfaca9fd0daecf93918e1cfc01c8a3d26ee7adcd"
|
||||
"checksum hash32 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "12d790435639c06a7b798af9e1e331ae245b7ef915b92f70a39b4cf8c00686af"
|
||||
"checksum heapless 0.4.4 (registry+https://github.com/rust-lang/crates.io-index)" = "e1ae80bbc62401ae8096976857172507cadbd2200f36670e5144634360a05959"
|
||||
"checksum log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c84ec4b527950aa83a329754b01dbe3f58361d1c5efacd1f6d68c494d08a17c6"
|
||||
"checksum heapless 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c6c7ce2e47016f34d17acbf2fe5f9e0337ea59d2ab8ceecd9405b2336ffaca9b"
|
||||
"checksum log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)" = "14b6052be84e6b71ab17edffc2eeabf5c2c3ae1fdb464aae35ac50c67a44e1f7"
|
||||
"checksum managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6"
|
||||
"checksum panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "2c14a66511ed17b6a8b4256b868d7fd207836d891db15eea5195dbcaf87e630f"
|
||||
"checksum panic-semihosting 0.5.2 (registry+https://github.com/rust-lang/crates.io-index)" = "97cfb37c1d3b5f0cc18bf14485018cccd13bdd24f7b5bfd456c1d8760afef824"
|
||||
"checksum proc-macro2 0.4.28 (registry+https://github.com/rust-lang/crates.io-index)" = "ba92c84f814b3f9a44c5cfca7d2ad77fa10710867d2bbb1b3d175ab5f47daa12"
|
||||
"checksum quote 0.6.12 (registry+https://github.com/rust-lang/crates.io-index)" = "faf4799c5d274f3868a4aae320a0a182cbd2baee377b378f080e16a23e9d80db"
|
||||
"checksum proc-macro2 0.4.30 (registry+https://github.com/rust-lang/crates.io-index)" = "cf3d2011ab5c909338f7887f4fc896d35932e29146c12c8d01da6b22a80ba759"
|
||||
"checksum quote 0.6.13 (registry+https://github.com/rust-lang/crates.io-index)" = "6ce23b6b870e8f94f81fb0a363d65d86675884b34a09043c81e5562f11c1f8e1"
|
||||
"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
|
||||
"checksum rand 0.5.6 (registry+https://github.com/rust-lang/crates.io-index)" = "c618c47cd3ebd209790115ab837de41425723956ad3ce2e6a7f09890947cacb9"
|
||||
"checksum rand_core 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "7a6fdeb83b075e8266dcc8762c22776f6877a63111121f5f8c7411e5be7eed4b"
|
||||
|
|
@ -344,13 +379,13 @@ dependencies = [
|
|||
"checksum rustc_version 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
|
||||
"checksum semver 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403"
|
||||
"checksum semver-parser 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
|
||||
"checksum serde 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "a72e9b96fa45ce22a4bc23da3858dfccfd60acd28a25bcd328a98fdd6bea43fd"
|
||||
"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=82fdca9)" = "<none>"
|
||||
"checksum serde_derive 1.0.91 (registry+https://github.com/rust-lang/crates.io-index)" = "101b495b109a3e3ca8c4cbe44cf62391527cdfb6ba15821c5ce80bcd5ea23f9f"
|
||||
"checksum serde 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "7fe5626ac617da2f2d9c48af5515a21d5a480dbd151e01bb1c355e26a3e68113"
|
||||
"checksum serde-json-core 0.0.1 (git+https://github.com/quartiq/serde-json-core.git?rev=fc764de)" = "<none>"
|
||||
"checksum serde_derive 1.0.98 (registry+https://github.com/rust-lang/crates.io-index)" = "01e69e1b8a631f245467ee275b8c757b818653c6d704cdbcaeb56b56767b529c"
|
||||
"checksum smoltcp 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fef582369edb298c6c41319a544ca9c4e83622f226055ccfcb35974fbb55ed34"
|
||||
"checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
|
||||
"checksum stm32h7 0.7.0 (registry+https://github.com/rust-lang/crates.io-index)" = "64173a3f8edb1bf9e17b14861695da2a7e6ca98afc99e0f249b62e4962cc478d"
|
||||
"checksum syn 0.15.33 (registry+https://github.com/rust-lang/crates.io-index)" = "ec52cd796e5f01d0067225a5392e70084acc4c0013fa71d55166d38a8b307836"
|
||||
"checksum stm32h7 0.8.0 (registry+https://github.com/rust-lang/crates.io-index)" = "63001af508d3332bd2dd81d4212b69e10f45e8f5435b7dab5def36178b9c1c17"
|
||||
"checksum syn 0.15.42 (registry+https://github.com/rust-lang/crates.io-index)" = "eadc09306ca51a40555dd6fc2b415538e9e18bc9f870e47b1a524a79fe2dcf5e"
|
||||
"checksum typenum 1.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "612d636f949607bdf9b123b4a6f6d966dedf3ff669f7f045890d3a4a73948169"
|
||||
"checksum unicode-xid 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "fc72304796d0818e357ead4e000d19c9c174ab23dc11093ac919054d20a6a7fc"
|
||||
"checksum vcell 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "45c297f0afb6928cd08ab1ff9d95e99392595ea25ae1b5ecf822ff8764e57a0d"
|
||||
|
|
|
|||
19
Cargo.toml
19
Cargo.toml
|
|
@ -30,25 +30,32 @@ default-target = "thumbv7em-none-eabihf"
|
|||
cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] }
|
||||
cortex-m-rt = { version = "0.6", features = ["device"] }
|
||||
cortex-m-log = { version = "0.5", features = ["log-integration"] }
|
||||
stm32h7 = { version = "0.7", features = ["stm32h7x3", "rt"] }
|
||||
log = "0.4"
|
||||
panic-abort = "0.3"
|
||||
panic-semihosting = { version = "0.5.2", optional = true }
|
||||
panic-semihosting = { version = "0.5", optional = true }
|
||||
serde = { version = "1.0", features = ["derive"], default-features = false }
|
||||
heapless = { version = "0.4" }
|
||||
heapless = { version = "0.5" }
|
||||
|
||||
[dependencies.serde-json-core]
|
||||
# version = "0.0"
|
||||
git = "https://github.com/quartiq/serde-json-core.git"
|
||||
rev = "82fdca9"
|
||||
rev = "fc764de"
|
||||
|
||||
[dependencies.stm32h7]
|
||||
version = "0.8"
|
||||
features = ["stm32h743", "rt"]
|
||||
|
||||
[dependencies.smoltcp]
|
||||
#git = "https://github.com/m-labs/smoltcp.git"
|
||||
#rev = "cd893e6"
|
||||
#rev = "0f61443"
|
||||
version = "0.5"
|
||||
features = ["proto-ipv4", "socket-tcp"]
|
||||
default-features = false
|
||||
|
||||
[dependencies.cortex-m-rtfm]
|
||||
git = "https://github.com/japaric/cortex-m-rtfm"
|
||||
rev = "fafeeb2"
|
||||
features = ["timer-queue"]
|
||||
|
||||
[features]
|
||||
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
|
||||
bkpt = [ ]
|
||||
|
|
|
|||
476
src/eth.rs
476
src/eth.rs
|
|
@ -1,6 +1,5 @@
|
|||
use core::{slice, cmp};
|
||||
use cortex_m;
|
||||
use stm32h7::stm32h7x3 as stm32;
|
||||
use stm32h7::stm32h743 as pac;
|
||||
use smoltcp::Result;
|
||||
use smoltcp::time::Instant;
|
||||
use smoltcp::wire::EthernetAddress;
|
||||
|
|
@ -87,7 +86,7 @@ use self::cr_consts::*;
|
|||
const CLOCK_RANGE: u8 = ETH_MACMIIAR_CR_HCLK_DIV_102;
|
||||
|
||||
|
||||
pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) {
|
||||
pub fn setup(rcc: &pac::RCC, syscfg: &pac::SYSCFG) {
|
||||
rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
|
||||
rcc.ahb1enr.modify(|_, w| {
|
||||
w.eth1macen().set_bit()
|
||||
|
|
@ -99,8 +98,8 @@ pub fn setup(rcc: &stm32::RCC, syscfg: &stm32::SYSCFG) {
|
|||
//rcc.ahb1rstr.modify(|_, w| w.eth1macrst().clear_bit());
|
||||
}
|
||||
|
||||
pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB,
|
||||
gpioc: &stm32::GPIOC, gpiog: &stm32::GPIOG) {
|
||||
pub fn setup_pins(gpioa: &pac::GPIOA, gpiob: &pac::GPIOB,
|
||||
gpioc: &pac::GPIOC, gpiog: &pac::GPIOG) {
|
||||
// PA1 RMII_REF_CLK
|
||||
gpioa.moder.modify(|_, w| w.moder1().alternate());
|
||||
gpioa.afrl.modify(|_, w| w.afr1().af11());
|
||||
|
|
@ -141,48 +140,40 @@ pub fn setup_pins(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB,
|
|||
|
||||
const PHY_ADDR: u8 = 0;
|
||||
|
||||
fn phy_read(reg_addr: u8) -> u16 {
|
||||
cortex_m::interrupt::free(|_cs| {
|
||||
let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() };
|
||||
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
mac.macmdioar.modify(|_, w| unsafe {
|
||||
w
|
||||
.pa().bits(PHY_ADDR)
|
||||
.rda().bits(reg_addr)
|
||||
.goc().bits(0b11) // read
|
||||
.cr().bits(CLOCK_RANGE)
|
||||
.mb().set_bit()
|
||||
});
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
mac.macmdiodr.read().md().bits()
|
||||
})
|
||||
fn phy_read(reg_addr: u8, mac: &pac::ETHERNET_MAC) -> u16 {
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
mac.macmdioar.modify(|_, w| unsafe {
|
||||
w
|
||||
.pa().bits(PHY_ADDR)
|
||||
.rda().bits(reg_addr)
|
||||
.goc().bits(0b11) // read
|
||||
.cr().bits(CLOCK_RANGE)
|
||||
.mb().set_bit()
|
||||
});
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
mac.macmdiodr.read().md().bits()
|
||||
}
|
||||
|
||||
fn phy_write(reg_addr: u8, reg_data: u16) {
|
||||
cortex_m::interrupt::free(|_cs| {
|
||||
let mac = unsafe { &*stm32::ETHERNET_MAC::ptr() };
|
||||
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) });
|
||||
mac.macmdioar.modify(|_, w| unsafe {
|
||||
w
|
||||
.pa().bits(PHY_ADDR)
|
||||
.rda().bits(reg_addr)
|
||||
.goc().bits(0b01) // write
|
||||
.cr().bits(CLOCK_RANGE)
|
||||
.mb().set_bit()
|
||||
});
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
})
|
||||
fn phy_write(reg_addr: u8, reg_data: u16, mac: &pac::ETHERNET_MAC) {
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
mac.macmdiodr.write(|w| unsafe { w.md().bits(reg_data) });
|
||||
mac.macmdioar.modify(|_, w| unsafe {
|
||||
w
|
||||
.pa().bits(PHY_ADDR)
|
||||
.rda().bits(reg_addr)
|
||||
.goc().bits(0b01) // write
|
||||
.cr().bits(CLOCK_RANGE)
|
||||
.mb().set_bit()
|
||||
});
|
||||
while mac.macmdioar.read().mb().bit_is_set() {}
|
||||
}
|
||||
|
||||
// Writes a value to an extended PHY register in MMD address space
|
||||
fn phy_write_ext(reg_addr: u16, reg_data: u16) {
|
||||
phy_write(PHY_REG_CTL, 0x0003); // set address
|
||||
phy_write(PHY_REG_ADDAR, reg_addr);
|
||||
phy_write(PHY_REG_CTL, 0x4003); // set data
|
||||
phy_write(PHY_REG_ADDAR, reg_data);
|
||||
fn phy_write_ext(reg_addr: u16, reg_data: u16, mac: &pac::ETHERNET_MAC) {
|
||||
phy_write(PHY_REG_CTL, 0x0003, mac); // set address
|
||||
phy_write(PHY_REG_ADDAR, reg_addr, mac);
|
||||
phy_write(PHY_REG_CTL, 0x4003, mac); // set data
|
||||
phy_write(PHY_REG_ADDAR, reg_data, mac);
|
||||
}
|
||||
|
||||
#[repr(align(4))]
|
||||
|
|
@ -201,7 +192,7 @@ impl RxRing {
|
|||
}
|
||||
}
|
||||
|
||||
fn init(&mut self) {
|
||||
unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
|
||||
assert_eq!(self.desc_buf[0].len() % 4, 0);
|
||||
assert_eq!(self.pkt_buf[0].len() % 4, 0);
|
||||
|
||||
|
|
@ -214,17 +205,10 @@ impl RxRing {
|
|||
}
|
||||
}
|
||||
|
||||
cortex_m::interrupt::free(|_cs| unsafe {
|
||||
let dma = &*stm32::ETHERNET_DMA::ptr();
|
||||
|
||||
dma.dmacrx_dlar.write(|w| {
|
||||
w.bits(&self.desc_buf as *const _ as u32)
|
||||
});
|
||||
|
||||
dma.dmacrx_rlr.write(|w| {
|
||||
w.rdrl().bits(self.desc_buf.len() as u16 - 1)
|
||||
});
|
||||
});
|
||||
let addr = &self.desc_buf as *const _ as u32;
|
||||
assert_eq!(addr & 0x3, 0);
|
||||
dma.dmacrx_dlar.write(|w| w.bits(addr));
|
||||
dma.dmacrx_rlr.write(|w| w.rdrl().bits(self.desc_buf.len() as u16 - 1));
|
||||
|
||||
self.cur_desc = 0;
|
||||
for _ in 0..self.desc_buf.len() {
|
||||
|
|
@ -259,11 +243,10 @@ impl RxRing {
|
|||
self.desc_buf[self.cur_desc][0] = addr as u32 & EMAC_DES0_BUF1AP;
|
||||
self.desc_buf[self.cur_desc][3] = EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN;
|
||||
|
||||
let addr = &self.desc_buf[self.cur_desc] as *const _;
|
||||
cortex_m::interrupt::free(|_cs| {
|
||||
let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() };
|
||||
dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr as u32) });
|
||||
});
|
||||
let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
|
||||
assert_eq!(addr & 0x3, 0);
|
||||
let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
|
||||
dma.dmacrx_dtpr.write(|w| unsafe { w.bits(addr) });
|
||||
|
||||
self.cur_desc = self.next_desc();
|
||||
}
|
||||
|
|
@ -285,7 +268,7 @@ impl TxRing {
|
|||
}
|
||||
}
|
||||
|
||||
fn init(&mut self) {
|
||||
unsafe fn init(&mut self, dma: &pac::ETHERNET_DMA) {
|
||||
assert_eq!(self.desc_buf[0].len() % 4, 0);
|
||||
assert_eq!(self.pkt_buf[0].len() % 4, 0);
|
||||
|
||||
|
|
@ -299,21 +282,13 @@ impl TxRing {
|
|||
}
|
||||
self.cur_desc = 0;
|
||||
|
||||
cortex_m::interrupt::free(|_cs| unsafe {
|
||||
let dma = &*stm32::ETHERNET_DMA::ptr();
|
||||
|
||||
dma.dmactx_dlar.write(|w| {
|
||||
w.bits(&self.desc_buf as *const _ as u32)
|
||||
});
|
||||
|
||||
dma.dmactx_rlr.write(|w| {
|
||||
w.tdrl().bits(self.desc_buf.len() as u16 - 1)
|
||||
});
|
||||
|
||||
dma.dmactx_dtpr.write(|w| {
|
||||
w.bits(&self.desc_buf[0] as *const _ as u32)
|
||||
});
|
||||
});
|
||||
let addr = &self.desc_buf as *const _ as u32;
|
||||
assert_eq!(addr & 0x3, 0);
|
||||
dma.dmactx_dlar.write(|w| w.bits(addr));
|
||||
dma.dmactx_rlr.write(|w| w.tdrl().bits(self.desc_buf.len() as u16 - 1));
|
||||
let addr = &self.desc_buf[0] as *const _ as u32;
|
||||
assert_eq!(addr & 0x3, 0);
|
||||
dma.dmactx_dtpr.write(|w| w.bits(addr));
|
||||
}
|
||||
|
||||
fn next_desc(&self) -> usize {
|
||||
|
|
@ -337,11 +312,10 @@ impl TxRing {
|
|||
self.desc_buf[self.cur_desc][3] = EMAC_DES3_OWN | EMAC_DES3_FD | EMAC_DES3_LD;
|
||||
self.cur_desc = self.next_desc();
|
||||
|
||||
let addr = &self.desc_buf[self.cur_desc] as *const _;
|
||||
cortex_m::interrupt::free(|_cs| {
|
||||
let dma = unsafe { &*stm32::ETHERNET_DMA::ptr() };
|
||||
dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr as u32) });
|
||||
});
|
||||
let addr = &self.desc_buf[self.cur_desc] as *const _ as u32;
|
||||
assert_eq!(addr & 0x3, 0);
|
||||
let dma = unsafe { pac::Peripherals::steal().ETHERNET_DMA };
|
||||
dma.dmactx_dtpr.write(|w| unsafe { w.bits(addr) });
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -356,180 +330,174 @@ impl Device {
|
|||
}
|
||||
|
||||
// After `init` is called, `Device` shall not be moved.
|
||||
pub unsafe fn init(&mut self, mac: EthernetAddress) {
|
||||
cortex_m::interrupt::free(|_cs| {
|
||||
let eth_mac = &*stm32::ETHERNET_MAC::ptr();
|
||||
let eth_dma = &*stm32::ETHERNET_DMA::ptr();
|
||||
let _eth_mmc = &*stm32::ETHERNET_MMC::ptr();
|
||||
let eth_mtl = &*stm32::ETHERNET_MTL::ptr();
|
||||
pub unsafe fn init(&mut self, mac: EthernetAddress,
|
||||
eth_mac: &pac::ETHERNET_MAC,
|
||||
eth_dma: &pac::ETHERNET_DMA,
|
||||
eth_mtl: &pac::ETHERNET_MTL,
|
||||
) {
|
||||
eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
|
||||
while eth_dma.dmamr.read().swr().bit_is_set() {}
|
||||
|
||||
eth_dma.dmamr.modify(|_, w| w.swr().set_bit());
|
||||
while eth_dma.dmamr.read().swr().bit_is_set() {}
|
||||
// 200 MHz
|
||||
eth_mac.mac1ustcr.modify(|_, w| w.tic_1us_cntr().bits(200 - 1));
|
||||
|
||||
// 200 MHz
|
||||
eth_mac.mac1ustcr.modify(|_, w| w.tic_1us_cntr().bits(200 - 1));
|
||||
|
||||
// Configuration Register
|
||||
eth_mac.maccr.modify(|_, w| {
|
||||
w
|
||||
.arpen().clear_bit()
|
||||
.ipc().set_bit()
|
||||
.ipg().bits(0b000) // 96 bit
|
||||
.ecrsfd().clear_bit()
|
||||
.dcrs().clear_bit()
|
||||
.bl().bits(0b00) // 19
|
||||
.prelen().bits(0b00) // 7
|
||||
// CRC stripping for Type frames
|
||||
.cst().set_bit()
|
||||
// Fast Ethernet speed
|
||||
.fes().set_bit()
|
||||
// Duplex mode
|
||||
.dm().set_bit()
|
||||
// Automatic pad/CRC stripping
|
||||
.acs().set_bit()
|
||||
// Retry disable in half-duplex mode
|
||||
.dr().set_bit()
|
||||
});
|
||||
eth_mac.macecr.modify(|_, w| {
|
||||
w
|
||||
.eipgen().clear_bit()
|
||||
.usp().clear_bit()
|
||||
.spen().clear_bit()
|
||||
.dcrcc().clear_bit()
|
||||
});
|
||||
// Set the MAC address
|
||||
eth_mac.maca0lr.write(|w|
|
||||
w.addrlo().bits( u32::from(mac.0[0]) |
|
||||
(u32::from(mac.0[1]) << 8) |
|
||||
(u32::from(mac.0[2]) << 16) |
|
||||
(u32::from(mac.0[3]) << 24))
|
||||
);
|
||||
eth_mac.maca0hr.write(|w|
|
||||
w.addrhi().bits( u16::from(mac.0[4]) |
|
||||
(u16::from(mac.0[5]) << 8))
|
||||
.ae().set_bit()
|
||||
//.sa().clear_bit()
|
||||
//.mbc().bits(0b000000)
|
||||
);
|
||||
// frame filter register
|
||||
eth_mac.macpfr.modify(|_, w| {
|
||||
w
|
||||
.dntu().clear_bit()
|
||||
.ipfe().clear_bit()
|
||||
.vtfe().clear_bit()
|
||||
.hpf().clear_bit()
|
||||
.saf().clear_bit()
|
||||
.saif().clear_bit()
|
||||
.pcf().bits(0b00)
|
||||
.dbf().clear_bit()
|
||||
.pm().clear_bit()
|
||||
.daif().clear_bit()
|
||||
.hmc().clear_bit()
|
||||
.huc().clear_bit()
|
||||
// Receive All
|
||||
.ra().clear_bit()
|
||||
// Promiscuous mode
|
||||
.pr().clear_bit()
|
||||
});
|
||||
eth_mac.macwtr.write(|w| w.pwe().clear_bit());
|
||||
// Flow Control Register
|
||||
eth_mac.macqtxfcr.modify(|_, w| {
|
||||
// Pause time
|
||||
w.pt().bits(0x100)
|
||||
});
|
||||
eth_mac.macrxfcr.modify(|_, w| w);
|
||||
eth_mtl.mtlrxqomr.modify(|_, w|
|
||||
w
|
||||
// Receive store and forward
|
||||
.rsf().set_bit()
|
||||
// Dropping of TCP/IP checksum error frames disable
|
||||
.dis_tcp_ef().clear_bit()
|
||||
// Forward error frames
|
||||
.fep().clear_bit()
|
||||
// Forward undersized good packets
|
||||
.fup().clear_bit()
|
||||
);
|
||||
eth_mtl.mtltxqomr.modify(|_, w| {
|
||||
w
|
||||
// Transmit store and forward
|
||||
.tsf().set_bit()
|
||||
});
|
||||
|
||||
if (phy_read(PHY_REG_ID1) != 0x0007) | (phy_read(PHY_REG_ID2) != 0xC131) {
|
||||
error!("PHY ID error!");
|
||||
}
|
||||
|
||||
phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET);
|
||||
while phy_read(PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {};
|
||||
phy_write_ext(PHY_REG_WUCSR, 0);
|
||||
phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M);
|
||||
/*
|
||||
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {};
|
||||
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {};
|
||||
while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED)
|
||||
!= PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {};
|
||||
*/
|
||||
|
||||
// operation mode register
|
||||
eth_dma.dmamr.modify(|_, w| {
|
||||
w
|
||||
.intm().clear_bit() // FIXME: bits(0b00)
|
||||
// Rx Tx priority ratio 1:1
|
||||
.pr().bits(0b000)
|
||||
.txpr().clear_bit()
|
||||
.da().clear_bit()
|
||||
});
|
||||
// bus mode register
|
||||
eth_dma.dmasbmr.modify(|_, w| {
|
||||
// Address-aligned beats
|
||||
w.aal().set_bit()
|
||||
// Fixed burst
|
||||
.fb().set_bit()
|
||||
});
|
||||
eth_dma.dmaccr.modify(|_, w| {
|
||||
w
|
||||
.dsl().bits(0)
|
||||
.pblx8().clear_bit()
|
||||
.mss().bits(536)
|
||||
});
|
||||
eth_dma.dmactx_cr.modify(|_, w| {
|
||||
w
|
||||
// Tx DMA PBL
|
||||
.txpbl().bits(32)
|
||||
.tse().clear_bit()
|
||||
// Operate on second frame
|
||||
.osf().clear_bit()
|
||||
});
|
||||
|
||||
eth_dma.dmacrx_cr.modify(|_, w| {
|
||||
w
|
||||
// receive buffer size
|
||||
.rbsz().bits(ETH_BUFFER_SIZE as u16)
|
||||
// Rx DMA PBL
|
||||
.rxpbl().bits(32)
|
||||
// Disable flushing of received frames
|
||||
.rpf().clear_bit()
|
||||
});
|
||||
|
||||
self.rx.init();
|
||||
self.tx.init();
|
||||
|
||||
// Manage MAC transmission and reception
|
||||
eth_mac.maccr.modify(|_, w| {
|
||||
w.re().bit(true) // Receiver Enable
|
||||
.te().bit(true) // Transmiter Enable
|
||||
});
|
||||
eth_mtl.mtltxqomr.modify(|_, w| w.ftq().set_bit());
|
||||
|
||||
// Manage DMA transmission and reception
|
||||
eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());
|
||||
eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit());
|
||||
|
||||
eth_dma.dmacsr.modify(|_, w|
|
||||
w.tps().set_bit()
|
||||
.rps().set_bit()
|
||||
);
|
||||
// Configuration Register
|
||||
eth_mac.maccr.modify(|_, w| {
|
||||
w
|
||||
.arpen().clear_bit()
|
||||
.ipc().set_bit()
|
||||
.ipg().bits(0b000) // 96 bit
|
||||
.ecrsfd().clear_bit()
|
||||
.dcrs().clear_bit()
|
||||
.bl().bits(0b00) // 19
|
||||
.prelen().bits(0b00) // 7
|
||||
// CRC stripping for Type frames
|
||||
.cst().set_bit()
|
||||
// Fast Ethernet speed
|
||||
.fes().set_bit()
|
||||
// Duplex mode
|
||||
.dm().set_bit()
|
||||
// Automatic pad/CRC stripping
|
||||
.acs().set_bit()
|
||||
// Retry disable in half-duplex mode
|
||||
.dr().set_bit()
|
||||
});
|
||||
eth_mac.macecr.modify(|_, w| {
|
||||
w
|
||||
.eipgen().clear_bit()
|
||||
.usp().clear_bit()
|
||||
.spen().clear_bit()
|
||||
.dcrcc().clear_bit()
|
||||
});
|
||||
// Set the MAC address
|
||||
eth_mac.maca0lr.write(|w|
|
||||
w.addrlo().bits( u32::from(mac.0[0]) |
|
||||
(u32::from(mac.0[1]) << 8) |
|
||||
(u32::from(mac.0[2]) << 16) |
|
||||
(u32::from(mac.0[3]) << 24))
|
||||
);
|
||||
eth_mac.maca0hr.write(|w|
|
||||
w.addrhi().bits( u16::from(mac.0[4]) |
|
||||
(u16::from(mac.0[5]) << 8))
|
||||
);
|
||||
// frame filter register
|
||||
eth_mac.macpfr.modify(|_, w| {
|
||||
w
|
||||
.dntu().clear_bit()
|
||||
.ipfe().clear_bit()
|
||||
.vtfe().clear_bit()
|
||||
.hpf().clear_bit()
|
||||
.saf().clear_bit()
|
||||
.saif().clear_bit()
|
||||
.pcf().bits(0b00)
|
||||
.dbf().clear_bit()
|
||||
.pm().clear_bit()
|
||||
.daif().clear_bit()
|
||||
.hmc().clear_bit()
|
||||
.huc().clear_bit()
|
||||
// Receive All
|
||||
.ra().clear_bit()
|
||||
// Promiscuous mode
|
||||
.pr().clear_bit()
|
||||
});
|
||||
eth_mac.macwtr.write(|w| w.pwe().clear_bit());
|
||||
// Flow Control Register
|
||||
eth_mac.macqtx_fcr.modify(|_, w| {
|
||||
// Pause time
|
||||
w.pt().bits(0x100)
|
||||
});
|
||||
eth_mac.macrx_fcr.modify(|_, w| w);
|
||||
eth_mtl.mtlrx_qomr.modify(|_, w|
|
||||
w
|
||||
// Receive store and forward
|
||||
.rsf().set_bit()
|
||||
// Dropping of TCP/IP checksum error frames disable
|
||||
.dis_tcp_ef().clear_bit()
|
||||
// Forward error frames
|
||||
.fep().clear_bit()
|
||||
// Forward undersized good packets
|
||||
.fup().clear_bit()
|
||||
);
|
||||
eth_mtl.mtltx_qomr.modify(|_, w| {
|
||||
w
|
||||
// Transmit store and forward
|
||||
.tsf().set_bit()
|
||||
});
|
||||
|
||||
if (phy_read(PHY_REG_ID1, eth_mac) != 0x0007) | (phy_read(PHY_REG_ID2, eth_mac) != 0xC131) {
|
||||
error!("PHY ID error!");
|
||||
}
|
||||
|
||||
phy_write(PHY_REG_BCR, PHY_REG_BCR_RESET, eth_mac);
|
||||
while phy_read(PHY_REG_BCR, eth_mac) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {};
|
||||
phy_write_ext(PHY_REG_WUCSR, 0, eth_mac);
|
||||
phy_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M, eth_mac);
|
||||
/*
|
||||
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_UP == 0 {};
|
||||
while phy_read(PHY_REG_BSR) & PHY_REG_BSR_ANDONE == 0 {};
|
||||
while phy_read(PHY_REG_SSR) & (PHY_REG_SSR_ANDONE | PHY_REG_SSR_SPEED)
|
||||
!= PHY_REG_SSR_ANDONE | PHY_REG_SSR_100BASE_FD {};
|
||||
*/
|
||||
|
||||
// operation mode register
|
||||
eth_dma.dmamr.modify(|_, w| {
|
||||
w
|
||||
.intm().bits(0b00)
|
||||
// Rx Tx priority ratio 1:1
|
||||
.pr().bits(0b000)
|
||||
.txpr().clear_bit()
|
||||
.da().clear_bit()
|
||||
});
|
||||
// bus mode register
|
||||
eth_dma.dmasbmr.modify(|_, w| {
|
||||
// Address-aligned beats
|
||||
w.aal().set_bit()
|
||||
// Fixed burst
|
||||
.fb().set_bit()
|
||||
});
|
||||
eth_dma.dmaccr.modify(|_, w| {
|
||||
w
|
||||
.dsl().bits(0)
|
||||
.pblx8().clear_bit()
|
||||
.mss().bits(536)
|
||||
});
|
||||
eth_dma.dmactx_cr.modify(|_, w| {
|
||||
w
|
||||
// Tx DMA PBL
|
||||
.txpbl().bits(32)
|
||||
.tse().clear_bit()
|
||||
// Operate on second frame
|
||||
.osf().clear_bit()
|
||||
});
|
||||
|
||||
eth_dma.dmacrx_cr.modify(|_, w| {
|
||||
w
|
||||
// receive buffer size
|
||||
.rbsz().bits(ETH_BUFFER_SIZE as u16)
|
||||
// Rx DMA PBL
|
||||
.rxpbl().bits(32)
|
||||
// Disable flushing of received frames
|
||||
.rpf().clear_bit()
|
||||
});
|
||||
|
||||
self.rx.init(eth_dma);
|
||||
self.tx.init(eth_dma);
|
||||
|
||||
// Manage MAC transmission and reception
|
||||
eth_mac.maccr.modify(|_, w| {
|
||||
w.re().bit(true) // Receiver Enable
|
||||
.te().bit(true) // Transmiter Enable
|
||||
});
|
||||
eth_mtl.mtltx_qomr.modify(|_, w| w.ftq().set_bit());
|
||||
|
||||
// Manage DMA transmission and reception
|
||||
eth_dma.dmactx_cr.modify(|_, w| w.st().set_bit());
|
||||
eth_dma.dmacrx_cr.modify(|_, w| w.sr().set_bit());
|
||||
|
||||
eth_dma.dmacsr.modify(|_, w|
|
||||
w.tps().set_bit()
|
||||
.rps().set_bit()
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -590,8 +558,7 @@ impl<'a> phy::TxToken for TxToken<'a> {
|
|||
}
|
||||
}
|
||||
|
||||
pub unsafe fn interrupt_handler() {
|
||||
let eth_dma = &*stm32::ETHERNET_DMA::ptr();
|
||||
pub unsafe fn interrupt_handler(eth_dma: &pac::ETHERNET_DMA) {
|
||||
eth_dma.dmacsr.write(|w|
|
||||
w
|
||||
.nis().set_bit()
|
||||
|
|
@ -600,8 +567,7 @@ pub unsafe fn interrupt_handler() {
|
|||
);
|
||||
}
|
||||
|
||||
pub unsafe fn enable_interrupt() {
|
||||
let eth_dma = &*stm32::ETHERNET_DMA::ptr();
|
||||
pub unsafe fn enable_interrupt(eth_dma: &pac::ETHERNET_DMA) {
|
||||
eth_dma.dmacier.modify(|_, w|
|
||||
w
|
||||
.nie().set_bit()
|
||||
|
|
|
|||
901
src/main.rs
901
src/main.rs
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue