pounder_test/src/bin/lockin-external.rs

181 lines
5.5 KiB
Rust
Raw Normal View History

#![deny(warnings)]
#![no_std]
#![no_main]
use stm32h7xx_hal as hal;
2021-02-06 01:59:22 +08:00
use stabilizer::{hardware, hardware::design_parameters};
use dsp::{lockin::Lockin, rpll::RPLL, Accu};
2021-01-20 21:29:29 +08:00
use hardware::{
Adc0Input, Adc1Input, Dac0Output, Dac1Output, InputStamper, AFE0, AFE1,
};
#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
const APP: () = {
struct Resources {
afes: (AFE0, AFE1),
adcs: (Adc0Input, Adc1Input),
dacs: (Dac0Output, Dac1Output),
net_interface: hardware::Ethernet,
2021-01-20 21:29:29 +08:00
timestamper: InputStamper,
2021-01-25 18:45:55 +08:00
pll: RPLL,
2021-01-21 21:55:33 +08:00
lockin: Lockin,
}
#[init]
fn init(c: init::Context) -> init::LateResources {
// Configure the microcontroller
let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device);
let pll = RPLL::new(
design_parameters::ADC_SAMPLE_TICKS_LOG2
+ design_parameters::SAMPLE_BUFFER_SIZE_LOG2,
);
2021-01-21 21:55:33 +08:00
// Enable ADC/DAC events
stabilizer.adcs.0.start();
stabilizer.adcs.1.start();
stabilizer.dacs.0.start();
stabilizer.dacs.1.start();
2021-01-21 21:55:33 +08:00
// Start recording digital input timestamps.
stabilizer.timestamp_timer.start();
2021-01-21 23:12:59 +08:00
// Start sampling ADCs.
stabilizer.adc_dac_timer.start();
2021-02-03 20:03:17 +08:00
// Enable the timestamper.
stabilizer.timestamper.start();
init::LateResources {
afes: stabilizer.afes,
adcs: stabilizer.adcs,
dacs: stabilizer.dacs,
net_interface: stabilizer.net.interface,
2021-01-20 21:29:29 +08:00
timestamper: stabilizer.timestamper,
2021-01-21 21:55:33 +08:00
pll,
2021-02-15 00:55:01 +08:00
lockin: Lockin::default(),
}
}
2021-02-02 22:50:31 +08:00
/// Main DSP processing routine.
///
2021-02-02 22:50:31 +08:00
/// See `dual-iir` for general notes on processing time and timing.
///
2021-02-02 22:50:31 +08:00
/// This is an implementation of a externally (DI0) referenced PLL lockin on the ADC0 signal.
/// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
/// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
2021-02-06 01:59:22 +08:00
#[task(binds=DMA1_STR4, resources=[adcs, dacs, lockin, timestamper, pll], priority=2)]
fn process(c: process::Context) {
let adc_samples = [
c.resources.adcs.0.acquire_buffer(),
c.resources.adcs.1.acquire_buffer(),
];
let dac_samples = [
c.resources.dacs.0.acquire_buffer(),
c.resources.dacs.1.acquire_buffer(),
];
2021-01-21 21:55:33 +08:00
let lockin = c.resources.lockin;
2021-02-02 21:34:48 +08:00
let timestamp = c
.resources
.timestamper
.latest_timestamp()
.unwrap_or(None) // Ignore data from timer capture overflows.
.map(|t| t as i32);
2021-01-25 18:45:55 +08:00
let (pll_phase, pll_frequency) = c.resources.pll.update(
2021-02-02 21:34:48 +08:00
timestamp,
2021-02-06 01:59:22 +08:00
21, // frequency settling time (log2 counter cycles), TODO: expose
21, // phase settling time, TODO: expose
2021-01-25 18:45:55 +08:00
);
2021-01-31 01:05:54 +08:00
// Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
2021-02-02 01:14:09 +08:00
let harmonic: i32 = -1; // TODO: expose
2021-02-08 18:26:58 +08:00
// Demodulation LO phase offset
2021-02-02 01:14:09 +08:00
let phase_offset: i32 = 0; // TODO: expose
2021-02-11 21:30:05 +08:00
// Log2 lowpass time constant
2021-02-12 18:06:59 +08:00
let time_constant: u8 = 6; // TODO: expose
2021-02-11 21:30:05 +08:00
2021-02-02 01:14:09 +08:00
let sample_frequency = ((pll_frequency
2021-02-15 15:51:19 +08:00
// half-up rounding bias
// .wrapping_add(1 << design_parameters::SAMPLE_BUFFER_SIZE_LOG2 - 1)
>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
as i32)
2021-02-01 00:10:03 +08:00
.wrapping_mul(harmonic);
2021-01-31 01:05:54 +08:00
let sample_phase =
2021-01-26 21:40:44 +08:00
phase_offset.wrapping_add(pll_phase.wrapping_mul(harmonic));
2021-02-02 01:14:09 +08:00
let output = adc_samples[0]
2021-02-01 20:42:21 +08:00
.iter()
.zip(Accu::new(sample_phase, sample_frequency))
// Convert to signed, MSB align the ADC sample.
.map(|(&sample, phase)| {
2021-02-11 21:30:05 +08:00
lockin.update(sample as i16, phase, time_constant)
2021-02-01 20:42:21 +08:00
})
.last()
2021-02-02 01:14:09 +08:00
.unwrap();
2021-02-06 01:59:22 +08:00
let conf = "frequency_discriminator";
let output = match conf {
2021-01-21 21:55:33 +08:00
// Convert from IQ to power and phase.
2021-02-12 06:15:32 +08:00
"power_phase" => [(output.log2() << 24) as _, output.arg()],
2021-02-12 01:14:28 +08:00
"frequency_discriminator" => [pll_frequency as _, output.arg()],
2021-02-12 18:06:59 +08:00
_ => [output.0, output.1],
2021-02-02 01:14:09 +08:00
};
// Convert to DAC data.
for i in 0..dac_samples[0].len() {
2021-02-06 01:59:22 +08:00
dac_samples[0][i] = (output[0] >> 16) as u16 ^ 0x8000;
dac_samples[1][i] = (output[1] >> 16) as u16 ^ 0x8000;
}
}
2021-02-06 01:59:22 +08:00
#[idle(resources=[afes])]
fn idle(_: idle::Context) -> ! {
loop {
2021-02-06 01:59:22 +08:00
// TODO: Implement network interface.
cortex_m::asm::wfi();
}
}
#[task(binds = ETH, priority = 1)]
fn eth(_: eth::Context) {
unsafe { hal::ethernet::interrupt_handler() }
}
#[task(binds = SPI2, priority = 3)]
fn spi2(_: spi2::Context) {
panic!("ADC0 input overrun");
}
#[task(binds = SPI3, priority = 3)]
fn spi3(_: spi3::Context) {
panic!("ADC0 input overrun");
}
#[task(binds = SPI4, priority = 3)]
fn spi4(_: spi4::Context) {
panic!("DAC0 output error");
}
#[task(binds = SPI5, priority = 3)]
fn spi5(_: spi5::Context) {
panic!("DAC1 output error");
}
extern "C" {
// hw interrupt handlers for RTIC to use for scheduling tasks
// one per priority
fn DCMI();
fn JPEG();
fn SDMMC();
}
};