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60 Commits

Author SHA1 Message Date
mwojcik c536a70890 satellite gateware: add rtio analyzer 2023-05-22 15:23:24 +08:00
mwojcik b747abe83c qc2: add 4 edge counters to the end of rtio 2023-04-03 12:25:07 +08:00
mwojcik 4b1ce1a6ff satellites: add rtio_dma, connect as cri master 2023-03-21 15:54:58 +08:00
mwojcik dce37a52aa KasliSoC satellite: fix serdes timing 2023-02-20 13:07:42 +08:00
mwojcik 46b2687d70 RTIO/SYS Clock merge 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2023-02-17 15:52:43 +08:00
mwojcik 19e60073de kasli_soc: ident = variant name 2022-10-21 11:55:24 +08:00
mwojcik efc432352e zc706: no syncrtio for master, fixes hangs (#188) 2022-05-03 14:36:10 +08:00
mwojcik def4d989cd kasli_soc: fix si5324 pins routed to GTX 2022-04-25 12:33:21 +08:00
mwojcik 1d731a3589 zc706 master: route sma clock to si5324 2022-04-13 16:35:52 +08:00
mwojcik 3cf86a6335 satellites: add rtio_crg cfg 2022-04-12 13:44:53 +08:00
occheung a22b13cc46 kasli_soc: forward SMA clkin 2022-03-09 12:43:47 +08:00
spaqin 85e5c08d7f kasli_soc: use si5324 in master 2022-03-04 13:17:53 +08:00
mwojcik 31fb2b388a Support for DRTIO 100MHz (#155) 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-12-03 17:19:42 +08:00
mwojcik e045837b67 zc706: not actually ultrascale 2021-11-29 12:48:45 +08:00
mwojcik ada3f2e704 drtio: reading still needs work buffer after all 2021-11-29 12:46:08 +08:00
mwojcik 8be5048cd3 upgrade to new clock configuration system (#152) 
As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version.

Reviewed-on: M-Labs/artiq-zynq#152
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-11-29 11:17:59 +08:00
mwojcik 0b27349ec4 dummy_spi -> pmod_spi 2021-10-14 16:37:13 +08:00
mwojcik 21eb1cab1a zc706: added dummy spi in place of sdio 2021-10-14 15:43:51 +08:00
mwojcik 3096daaaee zc706: removed nist_clock sdcard, put pmod instead 2021-10-14 15:01:38 +08:00
mwojcik 4fbfccf575 zc706: fix nist_qc2 extension, ams101 iostandard 2021-10-14 12:39:09 +08:00
mwojcik 5c40115945 make ZC706 RTIO channels consistent with KC705 
Reviewed-on: M-Labs/artiq-zynq#147
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-10-13 17:20:25 +08:00
mwojcik d04a7decfe removed simple variants from zc706 2021-10-08 11:07:12 +02:00
Sebastien Bourdeauducq 4fa824f42b kasli-soc: remove irrelevant comment 2021-10-08 16:13:17 +08:00
mwojcik ab0c205dd2 gateware: add DRTIO 
Reviewed-on: M-Labs/artiq-zynq#140
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-10-08 16:12:30 +08:00
Sebastien Bourdeauducq 18e05c91e1 zc706: si5324 is not needed for standalone target 2021-08-04 09:14:19 +08:00
mwojcik e3d3cb2311 si5324: bring on par with mainline ARTIQ (#132) 
si5324 driver in runtime should be now equal in function to the one in artiq.

kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.

Reviewed-on: M-Labs/artiq-zynq#132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-08-04 09:12:38 +08:00
Sebastien Bourdeauducq 8128dc0b56 Revert "kasli-soc: work around I2C breakage (#130)" 
This reverts commit f1fd55dee5.
 2021-07-30 16:55:06 +08:00
Sebastien Bourdeauducq 852123b42a kasli-soc: add RTIO LEDs 2021-05-30 20:40:53 +08:00
Sebastien Bourdeauducq f1fd55dee5 kasli-soc: work around I2C breakage (#130) 2021-05-29 17:13:41 +08:00
Sebastien Bourdeauducq 506c741238 support absence of gateware RTIO clock selection mux 2021-02-15 21:41:30 +08:00
Sebastien Bourdeauducq 8815f76114 kasli_soc: fix has_grabber 2021-02-15 21:41:02 +08:00
Sebastien Bourdeauducq ef18fa4c6d kasli_soc: add RTIO log channel 2021-02-15 19:56:59 +08:00
Sebastien Bourdeauducq faf9714e10 add demo build for Kasli-SoC 2021-02-15 19:52:13 +08:00
Sebastien Bourdeauducq 8d4e42be32 remove redpitaya and coraz7 support 2021-02-15 19:30:13 +08:00
Sebastien Bourdeauducq 4039431533 kasli_soc: fix eem iostandards 2021-02-07 22:34:29 +08:00
Sebastien Bourdeauducq 3f9bd06468 add Kasli-SoC generic gateware builder (WIP) 2021-02-07 14:44:32 +08:00
Astro 32048ead20 gateware/coraz7: remove unused VARIANTS 2020-11-14 02:24:29 +01:00
Astro 113c8eb0b8 add coraz7 + redpitaya targets 2020-11-13 20:17:18 +01:00
pca006132 03d9827a5a acpki: working 2020-09-09 21:24:49 +08:00
Sebastien Bourdeauducq 537f4968eb acpki: add legacy i_status/o_status registers 2020-08-04 17:31:35 +08:00
Sebastien Bourdeauducq 62988a580e acpki: update for combined RTIO channel/address 2020-08-04 17:28:15 +08:00
Sebastien Bourdeauducq 1e20259c36 fix acpki selection 2020-08-04 13:26:45 +08:00
Sebastien Bourdeauducq f8d4036451 add ACP kernel initiator 
Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
M-Labs/artiq-zynq#55

Work-in-progress, only gateware part and build system, untested.
 2020-08-04 13:15:26 +08:00
Sebastien Bourdeauducq 59cf2764ce dma: report AXI bus error 2020-07-21 12:47:20 +08:00
Sebastien Bourdeauducq 21135c6a41 analyzer: report AXI bus errors 2020-07-20 19:51:22 +08:00
Sebastien Bourdeauducq 523524c319 zc706: add RTIO log channels 2020-07-19 14:05:35 +08:00
Sebastien Bourdeauducq f69e41af5e gateware: fix VADJ I/O standard conflict 2020-07-16 17:58:31 +08:00
Sebastien Bourdeauducq 6a361893c2 gateware: make LEDs common to all variants 
Makes quick testing easier.
 2020-07-16 17:36:27 +08:00
Sebastien Bourdeauducq ae7ca22db9 dma: fix endianness issues 2020-07-16 17:27:08 +08:00
Sebastien Bourdeauducq 10a12245a3 analyzer: fix endianness issue 2020-07-16 17:10:09 +08:00