forked from M-Labs/artiq-zynq
removed simple variants from zc706
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0efa83e956
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@ -45,7 +45,7 @@ Note: if you are using Nix channels the first time, you need to be aware of this
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Pure build with Nix and execution on a remote JTAG server:
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```shell
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nix-build -A zc706-simple-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
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nix-build -A zc706-nist_clock-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock_satellite-jtag
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./remote_run.sh
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```
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@ -8,7 +8,7 @@ let
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vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
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# FSBL configuration supplied by Vivado 2020.1 for these boards:
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fsblTargets = ["zc702" "zc706" "zed"];
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sat_variants = ["satellite" "acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"];
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sat_variants = ["acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"];
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build = { target, variant, json ? null }: let
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szl = (import zynq-rs)."${target}-szl";
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fsbl = import "${zynq-rs}/nix/fsbl.nix" {
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@ -133,18 +133,12 @@ let
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);
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in
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(
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(build { target = "zc706"; variant = "simple"; }) //
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(build { target = "zc706"; variant = "master"; }) //
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(build { target = "zc706"; variant = "satellite"; }) //
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(build { target = "zc706"; variant = "nist_clock"; }) //
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(build { target = "zc706"; variant = "nist_clock_master"; }) //
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(build { target = "zc706"; variant = "nist_clock_satellite"; }) //
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(build { target = "zc706"; variant = "nist_qc2"; }) //
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(build { target = "zc706"; variant = "nist_qc2_master"; }) //
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(build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
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(build { target = "zc706"; variant = "acpki_simple"; }) //
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(build { target = "zc706"; variant = "acpki_master"; }) //
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(build { target = "zc706"; variant = "acpki_satellite"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
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@ -1,5 +1,5 @@
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TARGET := zc706
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GWARGS := -V simple
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GWARGS := -V nist_clock
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all: ../build/runtime.bin
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@ -427,22 +427,6 @@ class _SatelliteBase(SoCCore):
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self.csr_devices.append("routing_table")
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class _Simple_RTIO:
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def __init__(self):
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platform = self.platform
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class _NIST_CLOCK_RTIO:
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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@ -542,21 +526,6 @@ class _NIST_QC2_RTIO:
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self.add_rtio(rtio_channels)
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class Simple(ZC706, _Simple_RTIO):
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def __init__(self, acpki):
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ZC706.__init__(self, acpki)
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_Simple_RTIO.__init__(self)
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class Master(_MasterBase, _Simple_RTIO):
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def __init__(self, acpki):
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_MasterBase.__init__(self, acpki)
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_Simple_RTIO.__init__(self)
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class Satellite(_SatelliteBase, _Simple_RTIO):
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def __init__(self, acpki):
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_SatelliteBase.__init__(self, acpki)
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_Simple_RTIO.__init__(self)
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
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def __init__(self, acpki):
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ZC706.__init__(self, acpki)
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@ -589,8 +558,7 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
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_NIST_QC2_RTIO.__init__(self)
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VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite,
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NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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@ -625,9 +593,9 @@ def main():
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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parser.add_argument("-V", "--variant", default="simple",
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parser.add_argument("-V", "--variant", default="nist_clock",
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help="variant: "
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"[acpki_]simple/nist_clock/nist_qc2 "
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"[acpki_]nist_clock/nist_qc2[_master/_satellite] "
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"(default: %(default)s)")
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args = parser.parse_args()
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