23857eef63
allow toggling SED spread with flash config key
2024-07-09 18:11:20 +08:00
e1b2c45813
kasli_soc & zc706: Fix GTX Clock Path during INIT
2023-11-07 18:55:08 +08:00
49205eea17
satellite gateware: add kernel rtio to cri
2023-10-09 11:36:23 +08:00
1ccae0d442
consolidate all write..file() into config.py
2023-09-11 11:48:19 +08:00
2c19f4ac31
replace rustc_cfg[ ] & change write_rustc_cfg_file
2023-09-11 11:48:19 +08:00
4ae8557018
drtio: remame drtio_transceiver to gt_drtio
...
Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
2023-08-28 13:05:40 +08:00
63594d7e3d
update configuration of IBUFDS_GTE2
...
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 12:08:41 +08:00
ad076dd4e9
zc706: fix satellite analyzer target
2023-05-24 09:52:16 +08:00
c536a70890
satellite gateware: add rtio analyzer
2023-05-22 15:23:24 +08:00
b747abe83c
qc2: add 4 edge counters to the end of rtio
2023-04-03 12:25:07 +08:00
4b1ce1a6ff
satellites: add rtio_dma, connect as cri master
2023-03-21 15:54:58 +08:00
46b2687d70
RTIO/SYS Clock merge
...
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2023-02-17 15:52:43 +08:00
efc432352e
zc706: no syncrtio for master, fixes hangs ( #188 )
2022-05-03 14:36:10 +08:00
1d731a3589
zc706 master: route sma clock to si5324
2022-04-13 16:35:52 +08:00
3cf86a6335
satellites: add rtio_crg cfg
2022-04-12 13:44:53 +08:00
31fb2b388a
Support for DRTIO 100MHz ( #155 )
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Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-12-03 17:19:42 +08:00
e045837b67
zc706: not actually ultrascale
2021-11-29 12:48:45 +08:00
ada3f2e704
drtio: reading still needs work buffer after all
2021-11-29 12:46:08 +08:00
0b27349ec4
dummy_spi -> pmod_spi
2021-10-14 16:37:13 +08:00
21eb1cab1a
zc706: added dummy spi in place of sdio
2021-10-14 15:43:51 +08:00
3096daaaee
zc706: removed nist_clock sdcard, put pmod instead
2021-10-14 15:01:38 +08:00
4fbfccf575
zc706: fix nist_qc2 extension, ams101 iostandard
2021-10-14 12:39:09 +08:00
5c40115945
make ZC706 RTIO channels consistent with KC705
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Reviewed-on: M-Labs/artiq-zynq#147
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-13 17:20:25 +08:00
d04a7decfe
removed simple variants from zc706
2021-10-08 11:07:12 +02:00
ab0c205dd2
gateware: add DRTIO
...
Reviewed-on: M-Labs/artiq-zynq#140
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-08 16:12:30 +08:00
18e05c91e1
zc706: si5324 is not needed for standalone target
2021-08-04 09:14:19 +08:00
e3d3cb2311
si5324: bring on par with mainline ARTIQ ( #132 )
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si5324 driver in runtime should be now equal in function to the one in artiq.
kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.
Reviewed-on: M-Labs/artiq-zynq#132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-08-04 09:12:38 +08:00
506c741238
support absence of gateware RTIO clock selection mux
2021-02-15 21:41:30 +08:00
1e20259c36
fix acpki selection
2020-08-04 13:26:45 +08:00
f8d4036451
add ACP kernel initiator
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Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
M-Labs/artiq-zynq#55
Work-in-progress, only gateware part and build system, untested.
2020-08-04 13:15:26 +08:00
523524c319
zc706: add RTIO log channels
2020-07-19 14:05:35 +08:00
f69e41af5e
gateware: fix VADJ I/O standard conflict
2020-07-16 17:58:31 +08:00
6a361893c2
gateware: make LEDs common to all variants
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Makes quick testing easier.
2020-07-16 17:36:27 +08:00
8e758ecc17
add RTIO analyzer core (untested)
2020-07-15 23:06:34 +08:00
a7073edf79
add DMA core (untested)
2020-07-13 10:37:17 +08:00
e3ff21b1b5
create gateware folder
2020-07-11 17:49:54 +08:00
