- Dresden
- https://spaceboyz.net/~astro/
- Joined on
2019-04-18
caa69fda2e
main: refactor into boot
3279aab961
main: refactor into abort, panic, ram
92c274348f
zynq::eth: enable checksum offload
3eb7fce572
delint
b1472096ba
main: change IP address to 192.168.1.28/24
959bf8a245
zynq::eth: don't check_link_change if link already established
4d3b2ac7e5
zynq::ddr: use different data_bus_width for targets
cae02947bc
zynq::eth: remove all memory barriers
d360ec6dce
shell.nix: cd in shellHook
7efc95941b
default.nix: update rust nightly
afd96bd887
zynq::clocks: unlock slcr in enable_io()
261455877d
zynq::ddr: fix DDR 3x/2x setup, print clocks
ff96bf903b
zynq::ddr: only enable_ddr if no clock yet
d2df5652d0
Revert "zynq: replace unnecessary slcr::unlocked with new"
eb56dda44f
zynq::slcr::unlocked: fix comment
74c43b3477
zynq::eth::tx: clear entry.word1 for each packet
99a00e019b
zynq::eth: implement phy::extended_status, set clock for link speed
961e2e1dd0
zynq::{ddr, eth}: fix clock divisor calculation
04e816d99e
zynq::slcr: fix a bitfield index
5c62716a99
zynq::eth: switch rx and tx descriptor words to vcell
1f728686ff
rm ram, add linked_list_allocator on ddr
e248d3d3b1
zynq::ddr: optimize memtest
91bab76ab6
zynq::ddr: fix usable ram size
43501003f9
openocd/zc706: decimate `adapter_khz` for reliability
e45d1e78aa
tecpak: init
891bb0b31f
rpi: install screen, gdb, minicom
c3d6ee5627
artiq-full: build ptbal
aa6d631863
nixops: set up devboard users
e4a9bd5d6b
artiq-full: remove openocd-aarch64 (now handled via nixops)
7cdf6c0918
start implementation of a StaticAllocator
fc39885d3b
zynq::ddr: fix clock setup