M-Labs/zynq-rs
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zynq::ddr: only enable_ddr if no clock yet

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that's only an issue for the cora z7
This commit is contained in:
Astro 2019-11-06 23:04:35 +01:00
parent d2df5652d0
commit ff96bf903b
1 changed files with 4 additions and 1 deletions
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5
src/zynq/ddr/mod.rs
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@ -36,8 +36,11 @@ impl DdrRam {
/// 10.6.1 DDR Clock Initialization
fn clock_setup() -> CpuClocks {
let clocks = CpuClocks::get();
CpuClocks::enable_ddr(clocks.arm);
if clocks.ddr == 0 {
CpuClocks::enable_ddr(clocks.arm);
}
let clocks = CpuClocks::get();
println!("Clocks: {:?}", clocks);
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;