M-Labs
/
zynq-rs
11
0
Fork 15
Code Issues 6 Pull Requests 1 Releases Wiki Activity

GIC: fix wrong core target config when enabling interrupt #109

Merged
sb10q merged 1 commits from morgan/zynq-rs:irq_fix into master 2023-12-19 18:41:03 +08:00
Conversation 1 Commits 1 Files Changed 1 +1 -1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
libboard_zynq/src/gic.rs
View File

@ -115,7 +115,7 @@ impl InterruptController {
let m = (id.0 >> 2) as usize; let m = (id.0 >> 2) as usize;
let n = (8 * (id.0 & 3)) as usize; let n = (8 * (id.0 & 3)) as usize;
unsafe { unsafe {
self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1)); self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32));
} }
// sensitivity // sensitivity