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GIC: fix wrong core target config when enabling interrupt #109

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sb10q merged 1 commits from morgan/zynq-rs:irq_fix into master 2023-12-19 18:41:03 +08:00
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libboard_zynq/src/gic.rs
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@ -115,7 +115,7 @@ impl InterruptController {
let m = (id.0 >> 2) as usize;
let n = (8 * (id.0 & 3)) as usize;
unsafe {
self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1));
self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32));
}
// sensitivity