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d65398205f
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add a println! for convenience
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2019-06-20 00:30:18 +02:00 |
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b3b65f9b74
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eth: find Phy
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2019-06-19 00:21:17 +02:00 |
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54d0f3583d
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eth: fix io configuration
phy detection now works
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2019-06-18 23:10:35 +02:00 |
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1634513bc7
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mmu: align l1_table
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2019-06-18 19:18:47 +02:00 |
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9bebfb49bc
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begin MMU implementation
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2019-06-17 03:32:10 +02:00 |
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69b65b5f72
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cortex_a9 regs: allow defining bit fields
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2019-06-17 01:36:11 +02:00 |
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1e16beb707
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cortex_a9::regs: use crate::regs interface
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2019-06-12 00:20:23 +02:00 |
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81a892b618
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eth: recv_next()
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2019-06-10 02:44:29 +02:00 |
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f92ea3b99d
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eth: start_tx
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2019-06-09 20:28:33 +02:00 |
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f07a541c99
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eth: model rx/tx state with type parameters
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2019-06-09 20:10:41 +02:00 |
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74bd81f87f
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eth: add safety asserts
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2019-06-09 02:23:37 +02:00 |
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824e91e6cb
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eth: rx/tx desc list, start_rx
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2019-06-09 01:02:10 +02:00 |
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2d7fed6c59
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link again compiler_builtins
required for memset etc
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2019-06-09 01:00:58 +02:00 |
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d447f1cc45
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main: probe for PHYs
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2019-06-04 23:50:11 +02:00 |
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b9ca9324f0
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eth: fix initialization
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2019-06-04 23:48:33 +02:00 |
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6d15b82a3e
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cortex_a9::regs: init U bit for unaligned access
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2019-06-04 23:47:23 +02:00 |
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acf995d7da
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soft_reset: rm unreachable!
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2019-05-31 00:19:20 +02:00 |
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bf4f5108f4
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main: add UART_RATE
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2019-05-31 00:19:01 +02:00 |
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2df74cc055
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add static exception handling
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2019-05-30 20:30:19 +02:00 |
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b13bf72c17
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eth: begin phy communication
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2019-05-30 02:42:42 +02:00 |
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5b15bb5c0a
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main: make boot_core0() naked
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2019-05-30 02:41:44 +02:00 |
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c0610ad66a
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slcr: init gem* rclk/clk
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2019-05-30 02:26:19 +02:00 |
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ee7ae7f7cc
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slcr: add soft_rst()
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2019-05-30 00:24:51 +02:00 |
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b961526b97
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uart: remove type conversion from baud_rate_gen
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2019-05-30 00:22:45 +02:00 |
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a645d13f4b
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add uart panic handler
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2019-05-28 00:28:35 +02:00 |
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75bb755327
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extend linker script
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2019-05-27 22:38:10 +02:00 |
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d10ffe9eb9
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eth: setup mio_pins, configure net_cfg
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2019-05-25 03:06:39 +02:00 |
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51c39f032e
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run with the cora z7-10
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2019-05-25 02:38:48 +02:00 |
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b3da0e4c93
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slcr: define all mio_pin regs, typed io_type
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2019-05-25 02:34:58 +02:00 |
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6bf210366a
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regs: properly emit doc_comments
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2019-05-24 23:49:49 +02:00 |
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56c2f1d833
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eth: add net_status, phy_maint registers
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2019-05-24 00:20:59 +02:00 |
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ad77e3dc04
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eth: add net_cfg register
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2019-05-24 00:06:29 +02:00 |
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402b8c9ab1
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eth: no unsafe, note, add qbar register fields
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2019-05-23 23:18:36 +02:00 |
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1033648c3e
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add l1_cache_init()
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2019-05-23 19:05:06 +02:00 |
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179c617904
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add register_bits_typed! macro
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2019-05-23 18:29:05 +02:00 |
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785e726661
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RegisterW/RegisterRW: required &mut self for safety
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2019-05-23 18:01:18 +02:00 |
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62ca26fa71
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slcr: abstract with RegisterBlock
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2019-05-23 17:52:06 +02:00 |
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fd7fd0db14
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main: rm unused feature #![feature(global_asm)]
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2019-05-23 16:06:41 +02:00 |
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ea62d4fdec
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uart: make baudrate configurable, run at 115,200 baud
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2019-05-23 15:50:53 +02:00 |
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15883293ac
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uart: use div_round_closest in baud_rate_gen
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2019-05-23 15:37:07 +02:00 |
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7428fec200
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uart: add more channel_sts flags, wait for tx_fifo_empty() before sending
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2019-05-23 15:36:34 +02:00 |
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673d585d2f
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uart: extend regs
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2019-05-22 01:42:24 +02:00 |
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b296fc1d7f
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uart: add baud_rate_gen
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2019-05-22 01:42:00 +02:00 |
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43b6d3acd0
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uart: wait for reset
|
2019-05-21 02:53:59 +02:00 |
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47ec0116a9
|
use uart1 with more configuration
|
2019-05-21 01:30:54 +02:00 |
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5d02fe5c95
|
slcr: with_slcr() for unlock/lock
|
2019-05-21 01:30:17 +02:00 |
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351d18c10f
|
add register_at! macro
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2019-05-20 23:01:50 +02:00 |
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c88374eab1
|
fix SP init
|
2019-05-20 01:21:22 +02:00 |
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b754581452
|
eth: add regs and init
|
2019-05-07 19:28:33 +02:00 |
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7872e00182
|
uart: move logic outside regs
|
2019-05-07 17:46:37 +02:00 |
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275f297309
|
uart: impl fmt::Write
|
2019-05-07 16:45:31 +02:00 |
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ca9b10dce8
|
refactor regs macros for RO/WO/RW access
|
2019-05-07 00:32:45 +02:00 |
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1e540a1175
|
replace #[repr(packed)] with #[repr(C)]
avoids warnings regarding unsafe behaviour
|
2019-05-07 00:05:38 +02:00 |
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fdc6c38de6
|
enable_uart0(): add srcsel
|
2019-05-07 00:01:43 +02:00 |
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|
55957eea09
|
regs macros
|
2019-05-06 23:56:53 +02:00 |
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9b414e2408
|
PoC: boot, uart output in qemu
|
2019-05-05 14:56:23 +02:00 |
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