begin MMU implementation
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69b65b5f72
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9bebfb49bc
378
src/cortex_a9/mmu.rs
Normal file
378
src/cortex_a9/mmu.rs
Normal file
@ -0,0 +1,378 @@
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use core::mem::uninitialized;
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use bit_field::BitField;
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use super::{regs::*, asm};
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use crate::regs::RegisterW;
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#[derive(Copy, Clone)]
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#[repr(u8)]
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pub enum AccessDomain {
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NoAccess = 0b00,
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Client = 0b01,
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_Reserved = 0b10,
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Manager = 0b11,
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}
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const ACCESS_DOMAINS_SIZE: usize = 16;
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pub struct AccessDomains([AccessDomain; ACCESS_DOMAINS_SIZE]);
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impl AccessDomains {
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pub fn all_manager() -> Self {
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AccessDomains([AccessDomain::Manager; ACCESS_DOMAINS_SIZE])
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}
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}
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impl Into<u32> for AccessDomains {
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fn into(self) -> u32 {
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let mut result = 0;
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for (i, domain) in self.0.iter().enumerate() {
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result |= (*domain as u32) << (2 * i);
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}
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result
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}
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}
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#[derive(Copy, Clone)]
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#[repr(u8)]
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pub enum AccessPermissions {
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PermissionFault = 0,
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PrivilegedOnly,
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NoUserWrite,
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FullAccess,
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_Reserved1,
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PrivilegedReadOnly,
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ReadOnly,
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_Reserved2
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}
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impl AccessPermissions {
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fn ap(&self) -> u8 {
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(*self as u8) & 0b11
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}
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fn apx(&self) -> bool {
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(*self as u8) > (AccessPermissions::FullAccess as u8)
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}
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}
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pub struct L1Section {
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pub global: bool,
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pub shareable: bool,
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pub access: AccessPermissions,
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/// Type EXtension
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pub tex: u8,
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pub domain: u8,
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pub exec: bool,
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pub cacheable: bool,
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pub bufferable: bool,
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}
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#[repr(C)]
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#[derive(Clone, Copy)]
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pub struct L1Entry(u32);
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impl L1Entry {
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#[inline(always)]
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pub fn section(phys_base: u32, section: L1Section) -> Self {
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/// Must be aligned to 1 MB
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assert!(phys_base & 0x000f_ffff == 0);
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let mut entry = L1Entry(phys_base);
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entry.0.set_bits(0..=1, 0b10);
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entry.0.set_bit(2, section.bufferable);
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entry.0.set_bit(3, section.cacheable);
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entry.0.set_bit(4, !section.exec);
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assert!(section.domain < 16);
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entry.0.set_bits(5..=8, section.domain.into());
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entry.0.set_bits(10..=11, section.access.ap().into());
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assert!(section.tex < 8);
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entry.0.set_bits(12..=14, section.tex.into());
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entry.0.set_bit(15, section.access.apx());
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entry.0.set_bit(16, section.shareable);
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entry.0.set_bit(17, !section.global);
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entry
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}
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}
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const L1TABLE_SIZE: usize = 4096;
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#[repr(C, align(16384))]
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pub struct L1Table {
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table: [L1Entry; L1TABLE_SIZE]
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}
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impl L1Table {
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pub fn flat_layout() -> Self {
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let mut result = L1Table {
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table: unsafe { uninitialized() }
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};
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/* 0x00000000 - 0x00100000 (cacheable) */
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result.direct_mapped_section(0, L1Section {
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global: true,
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shareable: true,
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access: AccessPermissions::FullAccess,
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tex: 0b101,
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domain: 0b1111,
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exec: true,
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cacheable: false,
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bufferable: true,
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});
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/* (DDR cacheable) */
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for ddr in 1..=0x1ff {
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result.direct_mapped_section(ddr, L1Section {
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global: true,
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shareable: true,
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access: AccessPermissions::FullAccess,
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tex: 0b101,
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domain: 0b1111,
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exec: true,
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cacheable: true,
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bufferable: true,
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});
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}
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/* (unassigned/reserved). */
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for undef in 0x1ff..=0x3ff {
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result.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0x40000000 - 0x7fffffff (FPGA slave0) */
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for fpga_slave in 0x400..=0x7ff {
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result.direct_mapped_section(fpga_slave, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0x80000000 - 0xbfffffff (FPGA slave1) */
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for fpga_slave in 0x800..=0xbff {
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result.direct_mapped_section(fpga_slave, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0xc0000000 - 0xdfffffff (unassigned/reserved). */
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for undef in 0xc00..=0xdff {
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result.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0xe0000000 - 0xe02fffff (Memory mapped devices)
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* UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
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for mmapped_dev in 0xe00..=0xe02 {
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result.direct_mapped_section(mmapped_dev, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: true,
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cacheable: false,
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bufferable: true,
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});
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}
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/* 0xe0300000 - 0xe0ffffff (unassigned/reserved). */
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for undef in 0xe03..=0xe0f {
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result.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0xe1000000 - 0xe1ffffff (NAND) */
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for nand in 0xe10..=0xe1f {
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result.direct_mapped_section(nand, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: true,
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cacheable: false,
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bufferable: true,
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});
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}
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/* 0xe2000000 - 0xe3ffffff (NOR) */
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for nor in 0xe20..=0xe3f {
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result.direct_mapped_section(nor, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: true,
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cacheable: false,
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bufferable: true,
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});
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}
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/* 0xe4000000 - 0xe5ffffff (SRAM) */
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for nor in 0xe40..=0xe5f {
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result.direct_mapped_section(nor, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: true,
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cacheable: true,
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bufferable: true,
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});
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}
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/* 0xe6000000 - 0xf7ffffff (unassigned/reserved). */
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for undef in 0xe60..=0xf7f {
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result.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
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for apb in 0xf80..=0xf8f {
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result.direct_mapped_section(apb, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: true,
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cacheable: false,
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bufferable: true,
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});
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}
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/* 0xf9000000 - 0xfbffffff (unassigned/reserved). */
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for undef in 0xf90..=0xfbf {
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result.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
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for qspi in 0xfc0..=0xfdf {
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result.direct_mapped_section(qspi, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0,
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domain: 0,
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exec: true,
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cacheable: false,
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bufferable: true,
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});
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}
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/* 0xfe000000 - 0xffefffff (unassigned/reserved). */
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for undef in 0xfe0..=0xffe {
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result.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0xfff00000 - 0xffffffff (256K OCM when mapped to high address space) */
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result.direct_mapped_section(0xfff, L1Section {
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global: true,
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shareable: false,
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access: AccessPermissions::FullAccess,
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tex: 0b100,
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domain: 0,
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exec: true,
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cacheable: true,
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bufferable: true,
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});
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result
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}
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#[inline(always)]
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fn direct_mapped_section(&mut self, index: usize, section: L1Section) {
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assert!(index < L1TABLE_SIZE);
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let base = (index as u32) << 20;
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self.table[index] = L1Entry::section(base, section);
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}
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}
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pub fn with_mmu<F: FnMut() -> !>(l1table: &L1Table, mut f: F) -> ! {
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let domains = AccessDomains::all_manager();
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DACR.write(domains.into());
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let table_base = &l1table.table as *const _ as u32;
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assert!(table_base & 0x3fff == 0);
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TTBR0.write(
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TTBR0::zeroed()
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.irgn1(true)
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.s(true)
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// Outer Cacheable Write-Back, no allocate on write.
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.rgn(0b11)
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.irgn0(true)
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.table_base(table_base >> 14)
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);
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// Enable I-Cache and D-Cache
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SCTLR.write(
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SCTLR::zeroed()
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.m(true)
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.a(false)
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.c(true)
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.i(true)
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.unaligned(true)
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);
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// Synchronization barriers
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// Allows MMU to start
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asm::dsb();
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// Flushes pre-fetch buffer
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asm::isb();
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f();
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// table must live until here
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drop(l1table.table);
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unreachable!();
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}
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@ -1,4 +1,5 @@
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pub mod asm;
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pub mod regs;
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pub mod mmu;
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global_asm!(include_str!("exceptions.s"));
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@ -1,4 +1,4 @@
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use crate::register_bit;
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use crate::{register_bit, register_bits};
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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macro_rules! def_reg_r {
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@ -115,6 +115,28 @@ register_bit!(sctlr,
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/// Thumb Exception Enable
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te, 30);
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/// Domain Access Control Register
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pub struct DACR;
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def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
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def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
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/// Translation Table Base Register 0
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pub struct TTBR0;
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/// Translation Table Base Register 1
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pub struct TTBR1;
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def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
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def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
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def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
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def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
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wrap_reg!(ttbr);
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register_bits!(ttbr, table_base, u32, 14, 31);
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register_bit!(ttbr, irgn0, 6);
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register_bits!(ttbr, rgn, u8, 3, 4);
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register_bit!(ttbr,
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/// Translation table walk to shared memory?
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s, 1);
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register_bit!(ttbr, irgn1, 0);
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/// Invalidate TLBs
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#[inline(always)]
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pub fn tlbiall() {
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27
src/main.rs
27
src/main.rs
@ -4,6 +4,7 @@
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#![feature(global_asm)]
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#![feature(naked_functions)]
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#![feature(compiler_builtins_lib)]
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#![feature(never_type)]
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use core::fmt::Write;
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use core::mem::uninitialized;
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@ -19,7 +20,7 @@ use uart::Uart;
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mod eth;
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use crate::regs::{RegisterR, RegisterW};
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use crate::cortex_a9::{asm, regs::*};
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use crate::cortex_a9::{asm, regs::*, mmu};
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extern "C" {
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static mut __bss_start: u32;
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@ -51,8 +52,10 @@ unsafe fn boot_core0() -> ! {
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l1_cache_init();
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zero_bss(&mut __bss_start, &mut __bss_end);
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main();
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panic!("return from main");
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mmu::with_mmu(&mmu::L1Table::flat_layout(), || {
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main();
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panic!("return from main");
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});
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}
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fn l1_cache_init() {
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@ -64,24 +67,6 @@ fn l1_cache_init() {
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bpiall();
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// Invalidate D-Cache
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dccisw();
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// (Initialize MMU)
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// Enable I-Cache and D-Cache
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SCTLR.write(
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SCTLR::zeroed()
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.m(false)
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.a(false)
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.c(true)
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.i(true)
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.unaligned(true)
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);
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// Synchronization barriers
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// Allows MMU to start
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asm::dsb();
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// Flushes pre-fetch buffer
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asm::isb();
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}
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const UART_RATE: u32 = 115_200;
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