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b2c707d543
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ddr: remove superfluous _reg from register names
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2020-07-03 02:20:10 +02:00 |
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3841accd9c
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libboard_zynq: fix ddr memtest range
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2020-05-09 02:53:58 +02:00 |
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3e02980c20
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libboard_zynq: fix access to "full" 1022 MB on target_zc706
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2020-05-09 02:35:39 +02:00 |
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e047c2900b
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ddr: log clock info with debug level
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2020-05-01 12:27:43 +08:00 |
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877f2c34bd
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libboard_zynq: use log logging
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2020-05-01 01:46:42 +02:00 |
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8a98cef3fc
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libboard_zynq: fix some hw setup
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2020-04-03 00:17:25 +02:00 |
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ed52ead914
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cora ddr attempts
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2020-03-28 21:50:06 +01:00 |
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aae85981e2
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libboard_zynq::clocks: setup clock sources and cpu clock
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2020-01-23 23:15:10 +01:00 |
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cf1983e543
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split into lib{register, cortex_a9, board_zynq, board_zc706} crates
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2019-12-17 23:35:58 +01:00 |
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