M-Labs/zynq-rs
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libboard_zynq: fix some hw setup

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This commit is contained in:
Astro 2020-04-03 00:17:25 +02:00
parent de4e24adf4
commit 8a98cef3fc
4 changed files with 18 additions and 8 deletions
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16
libboard_zynq/src/ddr/mod.rs
View File

@ -1,6 +1,6 @@
use libregister::{RegisterR, RegisterW, RegisterRW};
use crate::{print, println};
use super::slcr;
use super::slcr::{self, DdriobVrefSel};
use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
mod regs;
@ -174,21 +174,25 @@ impl DdrRam {
);
#[cfg(feature = "target_zc706")]
slcr.ddriob_ddr_ctrl.modify(|_, w| w
.vref_ext_en_lower(true)
.vref_ext_en_upper(true)
.vref_int_en(true)
.vref_sel(DdriobVrefSel::Vref0_75V)
.vref_ext_en_lower(false)
.vref_ext_en_upper(false)
);
});
}
/// Reset DDR controller
fn reset_ddrc(&mut self) {
self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(false)
);
#[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit;
#[cfg(feature = "target_cora_z7_10")]
let width = regs::DataBusWidth::Width16bit;
self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(false)
.powerdown_en(false)
.data_bus_width(width)
);
self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(true)
.powerdown_en(false)

1
libboard_zynq/src/ddr/regs.rs
View File

@ -3,6 +3,7 @@ use volatile_register::{RO, RW};
use libregister::{register, register_bit, register_bits_typed};
#[allow(unused)]
#[derive(Clone, Copy)]
#[repr(u8)]
pub enum DataBusWidth {
Width32bit = 0b00,

7
libboard_zynq/src/flash/mod.rs
View File

@ -184,7 +184,6 @@ impl Flash<()> {
slcr::MioPin00::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
// Option: Add Second Serial Clock
@ -193,6 +192,7 @@ impl Flash<()> {
slcr::MioPin09::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
// Option: Add 4-bit Data
@ -201,21 +201,25 @@ impl Flash<()> {
slcr::MioPin10::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
slcr.mio_pin_11.write(
slcr::MioPin11::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
slcr.mio_pin_12.write(
slcr::MioPin12::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
slcr.mio_pin_13.write(
slcr::MioPin13::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
// Option: Add Feedback Output Clock
@ -224,6 +228,7 @@ impl Flash<()> {
slcr::MioPin08::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
});
}

2
libboard_zynq/src/slcr.rs
View File

@ -626,7 +626,7 @@ register_bit!(ddriob_ddr_ctrl, refio_en, 9);
register!(ddriob_dci_ctrl, DdriobDciCtrl, RW, u32);
register_bit!(ddriob_dci_ctrl, reset, 0);
register_bit!(ddriob_dci_ctrl, enable, 0);
register_bit!(ddriob_dci_ctrl, enable, 1);
register_bits!(ddriob_dci_ctrl, nref_opt1, u8, 6, 7);
register_bits!(ddriob_dci_ctrl, nref_opt2, u8, 8, 10);
register_bits!(ddriob_dci_ctrl, nref_opt4, u8, 11, 13);