Commit Graph

251 Commits

Author SHA1 Message Date
cae02947bc zynq::eth: remove all memory barriers
They were not the solution.
2019-11-10 23:52:55 +01:00
afd96bd887 zynq::clocks: unlock slcr in enable_io() 2019-11-07 00:13:50 +01:00
261455877d zynq::ddr: fix DDR 3x/2x setup, print clocks 2019-11-07 00:13:50 +01:00
ff96bf903b zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
2019-11-07 00:13:50 +01:00
d2df5652d0 Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4.
2019-11-07 00:13:50 +01:00
eb56dda44f zynq::slcr::unlocked: fix comment 2019-11-07 00:13:50 +01:00
6e50b32e80 openocd: configure SRST for digilent_jtag_smt2_nc + Zynq
Digilent docs say Zynq boards should connect it to GPIO2.

Closes #2
2019-11-05 12:36:07 +08:00
74c43b3477 zynq::eth::tx: clear entry.word1 for each packet 2019-11-04 02:31:40 +01:00
99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed 2019-11-04 02:30:00 +01:00
961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
2019-11-03 02:23:16 +01:00
04e816d99e zynq::slcr: fix a bitfield index
that didn't solve our problems.
2019-11-03 02:01:42 +01:00
6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new 2019-10-31 20:48:07 +01:00
54e4b9281f main: rewrap linked_list_allocator 2019-10-31 19:21:02 +01:00
f688eb83ab default.nix: update cargoSha256 2019-10-31 03:19:39 +01:00
5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
2019-10-31 03:15:13 +01:00
1f728686ff rm ram, add linked_list_allocator on ddr 2019-10-31 01:41:10 +01:00
e248d3d3b1 zynq::ddr: optimize memtest 2019-10-31 01:32:45 +01:00
91bab76ab6 zynq::ddr: fix usable ram size 2019-10-31 01:27:49 +01:00
43501003f9 openocd/zc706: decimate adapter_khz for reliability 2019-10-31 00:28:19 +01:00
ceeaa6427e zynq::ddr: fix typo 2019-10-28 23:58:25 +01:00
7cdf6c0918 start implementation of a StaticAllocator 2019-10-28 00:43:57 +01:00
fc39885d3b zynq::ddr: fix clock setup 2019-10-28 00:43:09 +01:00
f199ac68b4 zynq::ddr: don't overwrite slcr.ddr_pll_ctrl 2019-10-27 22:54:34 +01:00
637bb35f43 zynq::ddr: fix memtest progress calculation 2019-10-27 20:38:35 +01:00
85bd506132 zynq::ddr: parameters 2019-10-27 20:38:06 +01:00
27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
2019-10-27 20:30:56 +01:00
9b4f07f37c zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00
e61d1268ac zynq::slcr: doc, fix 2019-10-25 23:18:18 +02:00
a4d3360a70 zynq::slcr: implement Display for PllStatus 2019-10-25 20:38:10 +02:00
838434cdec zynq::ddr: wait for init 2019-10-25 19:15:22 +02:00
4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main 2019-10-24 01:39:14 +02:00
a8886de067 zynq::ddr: implement configure_iob() 2019-10-24 01:24:12 +02:00
afda48e3fe zynq::ddr: add clock_setup(), calibrate_iob_impedance() 2019-10-22 01:25:35 +02:00
c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
9d725bcf0f zynq::ddr: init with clock setup 2019-10-21 22:12:10 +02:00
58cf9833cc slcr: implement PllCfg and DdrClkCtrl 2019-10-21 22:10:51 +02:00
83b8bb096a add zynq::axi_gp 2019-10-19 01:46:43 +02:00
b541160f38 add zynq::axi_hp 2019-10-18 23:46:00 +02:00
Björn Stein
1804c4c6e8 cortex_a9: add proper L1 cache invalidation 2019-10-18 00:11:51 +02:00
Björn Stein
d87b874b21 eth: add memory barriers, reorder access 2019-10-18 00:04:22 +02:00
Björn Stein
9053166acc eth: increase desc list safety 2019-10-18 00:03:17 +02:00
4e9c38527e rm debug, delint 2019-09-29 03:01:24 +02:00
a76214cb9d eth: split into Eth and EthInner 2019-09-29 02:58:17 +02:00
0f6bc68d1f eth: prepare link change detection 2019-09-29 02:30:03 +02:00
378755a0ce main: bump RX_LEN/TX_LEN to 2 2019-09-29 01:40:38 +02:00
644cc64524 eth: align DescEntries 2019-09-29 01:39:12 +02:00
f9cc561144 link.x: fix __stack_start
This fixes the memory corruption problem.
2019-09-29 01:38:47 +02:00
06bc7ba809 openocd: fix PL_TAPID for both targets
Fixes Gitea issue #1
2019-09-28 23:53:40 +02:00
d5334cc083 default.nix: fix use of rustManifest
part of Gitea issue #4
2019-09-26 23:34:06 +02:00
20249cf2da default.nix: build zc706 2019-09-26 17:54:37 +02:00