openocd SRST error #2

New Issue

sb10q · 2019-08-20T13:34:02+08:00

sb10q commented

2019-08-20 13:34:02 +08:00

$ openocd -f zc706.cfg  
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 10000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Zynq CPU1.
...
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Error: Can't assert SRST: nSRST signal is not defined
Info : JTAG tap: zynq.tap tap/device found: 0x23731093 (mfg: 0x049 (Xilinx), part: 0x3731, ver: 0x2)

```text $ openocd -f zc706.cfg Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html none separate adapter speed: 10000 kHz Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. Zynq CPU1. ... MMU: disabled, D-Cache: disabled, I-Cache: disabled Error: Can't assert SRST: nSRST signal is not defined Info : JTAG tap: zynq.tap tap/device found: 0x23731093 (mfg: 0x049 (Xilinx), part: 0x3731, ver: 0x2) ```

astro commented

2019-09-29 05:58:30 +08:00

These FTDI layouts don't include an nSRST signal. The digilent cfgs actually specify reset_config none. That prevents any reset from working. Hence it's currently overwritten with a reset_config that just emits a warning.

Continuing to investigate...

These FTDI layouts don't include an nSRST signal. The digilent cfgs actually specify `reset_config none`. That prevents any reset from working. Hence it's currently overwritten with a reset_config that just emits a warning. Continuing to investigate...

sb10q commented

2019-10-30 12:54:15 +08:00

Let's find out how Vivado handles this.

sb10q referenced this issue from a commit

2019-11-05 12:36:45 +08:00

openocd: configure SRST for digilent_jtag_smt2_nc + Zynq Digilent docs say Zynq boards should connect it to GPIO2. Closes #2

sb10q closed this issue

2019-11-05 12:36:45 +08:00

Sign in to join this conversation.